開發模組 (EVM) 的 GUI
TPS60252
- 3.0 V to 6.0 V Input Voltage Range
- ×1 and ×1.5 Charge Pump
- Fully Programmable Current with I2C
- 64 Dimming Steps with 25mA Maximum (Sub and Main Display Banks)
- 4 Dimming Steps with 80mA Maximum (DM5 for Auxiliary Application)
- 2% Current Matching for Sub LEDs at Light Load Condition (Each 100µA)
- 750 kHz Charge Pump Frequency
- Continuous 230mA Maximum Output Current
- Auto Switching Between ×1 and ×1.5 Mode for Maximum Efficiency
- Built-in Soft Start and Current Limit
- Open Lamp Detection
- 16-Pin 3mm x 3mm QFN
- TPS60250 (I2C Slave Address: 1110111)
- TPS60252 (I2C Slave Address: 1110110)
- APPLICATIONS
- Cellular Phones
- PDA, PMP, GPS (Up To 4 Inch LCD Display)
- Multidisplay Handheld Devices
The TPS60250/2 are high efficiency, constant frequency charge pump DC/DC converters that use dual mode 1× and 1.5× conversions to maximize efficiency over the input voltage range. The devices drive up to five white LEDs for the main display and up to two white LEDs for the sub display with regulated constant current for uniform intensity. By utilizing adaptive 1×/1.5× charge pump modes and very low-dropout current regulators, the TPS60250/2 achieve high efficiency over the full 1-cell lithium-battery input voltage range.
Four enable inputs, ENmain, ENsub1, ENsub2, and ENaux, available through the I2C, are used for simple on/off controls for the independent main, sub1, sub2, and DM5 displays, respectively. To lower the operating current when using one sub display LED, the devices provide completely separate operation for the sub display LEDs.
The TPS60250/2 are available in a 16-pin 3mm x 3mm thin QFN.
技術文件
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檢視所有 4 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | High Efficiency Charge Pump for 7 WLEDs with I2C Interface datasheet (Rev. C) | 2008年 4月 23日 | |
| White paper | Common LED Functions and LED Driver Design Considerations | 2020年 9月 21日 | ||
| Application note | Performing Accurate PFM Mode Efficiency Measurements (Rev. A) | 2018年 12月 11日 | ||
| Application note | Extending the Soft Start Time Without a Soft Start Pin (Rev. B) | 2017年 6月 15日 |
設計與開發
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模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RTE) | 16 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點