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DDR 記憶體電源 IC

TPS7H3301-SP

現行

抗輻射 QMLV、2.3-V 至 3.5-V 輸入、3-A 汲極和源極 DDR 終端 LDO 穩壓器

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產品規格表

TPS7H3301-SP

現行
產品規格表 立即訂購

產品詳細資料

DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
DDR memory type DDR2, DDR3, DDR4 Control mode S3, S4/S5 Iout VTT (max) (A) 3 Iq (typ) (mA) 18 Output VREF, VTT Vin (min) (V) 0.9 Vin (max) (V) 3.5 Features Complete Solution, Shutdown Pin for S3 Rating Space Operating temperature range (°C) -55 to 125 Regulator type Linear Regulator Vin bias (max) (V) 3.5 Vin bias (min) (V) 2.375 Vout VTT (min) (V) 0.6
CFP (HKR) 16 105.6 mm² 11 x 9.6
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated
  • 5962R14228(1):
    • Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
    • Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
    • Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
  • Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
  • Input voltage: supports a 2.5-V and 3.3-V rail(3)
  • Separate low-voltage input (VLDOIN) down to 0.9 V for improved power efficiency(3)
  • 3-A sink and source termination regulator includes droop compensation
  • Enable input and power-good output for power supply sequencing
  • VTT termination regulator
    • Output voltage range: 0.5 to 1.75 V
    • 3-A sink and source current
  • Integrated precision voltage divider network with sense input
  • Remote sensing (VTTSNS)
  • VTTREF buffered reference

    • 49% to 51% accuracy with respect to VDDQSNS (±3 mA)

    • ±10-mA sink and source current
  • Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.
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類型 標題 日期
* Data sheet TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator With Built-In VTTREF Buffer datasheet (Rev. C) PDF | HTML 2024年 9月 27日
* Radiation & reliability report TPS7H3301-SP and TPS7H3302-SP Single-Event Effects Radiation Report (Rev. C) 2024年 1月 26日
* Radiation & reliability report TPS7H3301-SP Neutron Displacement Damage Characterization 2019年 4月 12日
* SMD TPS7H3301-SP SMD 5962-14228 2016年 7月 8日
* Radiation & reliability report TPS7H3301-SP Total Ionizing Dose Radiation Report 2016年 7月 1日
Application brief DLA Approved Optimizations for QML Products (Rev. B) PDF | HTML 2024年 5月 17日
Selection guide TI Space Products (Rev. J) 2024年 2月 12日
Application note Using Space Grade Power Components to Power AMD Kintex XQRKU060 FPGA PDF | HTML 2023年 11月 8日
Application note Using Space Grade Power Components to Power Microchip RT PolarFire FPGA PDF | HTML 2023年 9月 20日
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023年 8月 31日
Application note QML flow, its importance, and obtaining lot information (Rev. C) 2023年 8月 30日
Application note Space Grade Power Solution for Microsemi RTG4 PDF | HTML 2023年 5月 2日
Application note TI Space Rated Power Solution for Microsemi® RTG4™ FPGA (Rev. B) PDF | HTML 2023年 1月 19日
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022年 11月 17日
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022年 10月 19日
EVM User's guide TPS7H3301EVM-CVAL User's Guide (Rev. B) 2020年 10月 30日
Application note DLA Standard Microcircuit Drawings (SMD) and JAN Part Numbers Primer 2020年 8月 21日
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
Application note Hermetic Package Reflow Profiles, Termination Finishes, and Lead Trim and Form PDF | HTML 2020年 5月 18日
E-book Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
Application note External Soft-Start Circuit for TPS7H3301-SP Power-Up Sequencing Applications 2016年 7月 7日
Technical article 7 things to know about spacecraft subsystems before your next trip to Mars PDF | HTML 2016年 7月 6日

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開發板

TPS7H3301EVM-CVAL — TPS7H3301-SP DDR 終端評估模組

TPS7H3301-SP source/sink Double Data Rate (DDR) termination regulator designed to support system needs for low noise applications.

Integrated solution with reduced system solution size, improved efficiency, and simple system design integration.

使用指南: PDF
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開發套件

ALPHA-XILINX-KU060-SPACE — 附帶 TI 電源且適用於 Xilinx® Kintex® UltraScale™ XQRKU060 FPGA 的 Alpha Data® 主機板

This is a development kit for the Xilinx® XQRKU060 FPGA with industrial -1 speed grade. ADA-SDEV-KIT2 has a modular board design with a XRTC-compatible configuration module, two FMC connectors, DDR3 DRAM, system monitoring, and space-grade TI power management and temperature-sensing solutions.
從：Alpha Data Parallel Systems Ltd.
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模擬型號

TPS7H3301-SP PSpice Transient Model (Rev. B)

SLVMBF1B.ZIP (116 KB) - PSpice Model
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模擬型號

TPS7H3301-SP Unencrypted PSPICE Transient Model

SLVMDD2.ZIP (196 KB) - PSpice Model
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計算工具

SLVC650 — TPS7H3301-SP Calculator

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產品
DDR 記憶體電源 IC
TPS7H3301-SP — 抗輻射 QMLV、2.3-V 至 3.5-V 輸入、3-A 汲極和源極 DDR 終端 LDO 穩壓器
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