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UCC27444-Q1

現行

具 -5-V 輸入功能的車用 4-A 雙通道低壓側閘極驅動器

產品詳細資料

Number of channels 2 Power switch IGBT, MOSFET Peak output current (A) 4 Input supply voltage (min) (V) 4 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 125 Fall time (ns) 7 Input threshold CMOS, TTL Channel input logic Non-Inverting Input negative voltage (V) -5 Rating Automotive Driver configuration Non-Inverting
Number of channels 2 Power switch IGBT, MOSFET Peak output current (A) 4 Input supply voltage (min) (V) 4 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 125 Fall time (ns) 7 Input threshold CMOS, TTL Channel input logic Non-Inverting Input negative voltage (V) -5 Rating Automotive Driver configuration Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • Typical 4-A peak source and sink drive current for each channel
  • INA and INB input pins capable of handling –5 V
  • Absolute maximum VDD voltage 20 V
  • Wide VDD operating range from 4.5 V to 18 V
  • Two independent gate drive channels
  • Independent enable function for each output
  • Fast propagation delays (18-ns typical)
  • Fast rise and fall times (11-ns and 7-ns typical)
  • 1-ns typical delay matching between the two channels
  • SOIC8 and VSSOP8 PowerPAD™ package options
  • Operating junction temperature range of –40°C to 125°C
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • Typical 4-A peak source and sink drive current for each channel
  • INA and INB input pins capable of handling –5 V
  • Absolute maximum VDD voltage 20 V
  • Wide VDD operating range from 4.5 V to 18 V
  • Two independent gate drive channels
  • Independent enable function for each output
  • Fast propagation delays (18-ns typical)
  • Fast rise and fall times (11-ns and 7-ns typical)
  • 1-ns typical delay matching between the two channels
  • SOIC8 and VSSOP8 PowerPAD™ package options
  • Operating junction temperature range of –40°C to 125°C

The UCC27444-Q1 is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET and GaN power switches. UCC27444-Q1 has a typical peak drive strength of 4 A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The device’s fast propagation delay (18-ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.

The UCC27444-Q1 can handle –5 V at its INx inputs, which improves robustness in systems with moderate ground bouncing. The inputs can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The device’s transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.

The UCC27444-Q1 also features low voltage operation and power on reset (POR) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.

The UCC27444-Q1 is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET and GaN power switches. UCC27444-Q1 has a typical peak drive strength of 4 A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The device’s fast propagation delay (18-ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.

The UCC27444-Q1 can handle –5 V at its INx inputs, which improves robustness in systems with moderate ground bouncing. The inputs can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The device’s transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.

The UCC27444-Q1 also features low voltage operation and power on reset (POR) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.

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類型 標題 日期
* Data sheet UCC27444-Q1 20-V, 4-A Dual-Channel Low-Side Gate Driver with –5-V Input Capability For Automotive Applications datasheet (Rev. A) PDF | HTML 2023年 7月 20日
Application note Why use a Gate Drive Transformer? PDF | HTML 2024年 3月 4日
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 2024年 1月 22日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 2019年 1月 18日

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