計算工具
UCC37322
- Industry-Standard Pin-Out With Addition of Enable Function
- High-Peak Current Drive Capability of ±9 A at theMiller plateau region Using TrueDrive
- Efficient Constant Current Sourcing Using a Unique BiPolar and CMOS Output Stage
- TTL/CMOS Compatible Inputs Independent of Supply Voltage
- 20-ns Typical Rise and Fall Times With 10-nF Load
- Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising
- 4-V to 15-V Supply Voltage
- Available in Thermally Enhanced MSOP PowerPAD™ Package With 4.7°C/W θjc
- Rated From –40°C to +105°C
- Pb-Free Finish (CU NIPDAU) on 8-pin SOIC and PDIP Packages
The UCC2732x/UCC3732x family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity, and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322).
技術文件
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檢視所有 9 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC2732x/UCC3732x Single 9-A High-Speed Low-Side Mosfet Driver With Enable datasheet (Rev. I) | PDF | HTML | 2023年 11月 28日 |
| Application note | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024年 1月 22日 | |
| Application note | Using a Single-Output Gate-Driver for High-Side or Low-Side Drive (Rev. B) | PDF | HTML | 2023年 9月 8日 | |
| Application note | Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver | PDF | HTML | 2021年 11月 10日 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
| Application brief | How to overcome negative voltage transients on low-side gate drivers' inputs | 2019年 1月 18日 | ||
| More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 2018年 10月 29日 | ||
| Selection guide | Power Management Guide 2018 (Rev. R) | 2018年 6月 25日 |
設計與開發
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模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HVSSOP (DGN) | 8 | Ultra Librarian |
| PDIP (P) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。