UCC44273
- 5-pin DBV (SOT-23) package option
- Industry standard pinout
- 4-A peak source and sink symmetrical drive
- Ability to handle negative voltages (–5 V) at inputs
- Fast propagation delays (13 ns typical)
- Fast rise and fall times (9 ns and 7 ns typical)
- 4.5-V to 18-V single supply range
- Outputs held low during VDD UVLO (ensures glitch-free operation at power up and power down)
- TTL and CMOS compatible input-logic threshold (independent of supply voltage)
- Hysteretic-logic thresholds for high-noise immunity
- Output held low when input pin is floating
- Input pin absolute maximum voltage levels not restricted by VDD pin bias supply voltage
- Operating temperature range of –40°C to 140°C
The UCC44273 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC44273 is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.
The UCC44273 device is capable of handling –5 V at the input pins. The UCC44273 provides 4-A source and 4-A sink (symmetrical drive) peak-drive current capability at VDD = 12 V.
The UCC44273 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –40°C to 140°C. Internal Undervoltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range.
The input pin threshold of the UCC44273 device is based on TTL and CMOS compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC44273 4-A, 4-A Single-Channel Low-Side Driver with 5-V UVLO datasheet | PDF | HTML | 2023年 10月 4日 |
| Application note | Selecting Gate Drivers for HVAC Systems | PDF | HTML | 2024年 4月 4日 | |
| Application note | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024年 1月 22日 | |
| Application note | How to Choose a Gate Driver for DC Motor Drives | PDF | HTML | 2023年 10月 5日 | |
| Application note | Using a Single-Output Gate-Driver for High-Side or Low-Side Drive (Rev. B) | PDF | HTML | 2023年 9月 8日 | |
| Application note | Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver | PDF | HTML | 2021年 11月 10日 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
| Application brief | How to overcome negative voltage transients on low-side gate drivers' inputs | 2019年 1月 18日 | ||
| Application brief | Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole | 2018年 3月 16日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |
訂購與品質
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- 材料內容
- 認證摘要
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