Herramienta de cálculo
TPS544C25
Convertidor reductor SWIFT™ síncrono de 4.5 V a 18 V y 30 A con PMBus y sincronización de frecuencia
Hoja de datos
TPS544C25
- PMBus 1.2 Compliant Converters: 20 A and 30 A
- Input Voltage Range: 4.5 V to 18 V
- Output Voltage Range: 0.5 V to 5.5 V
- 5 mm × 7 mm LQFN Package
- Single Thermal Pad
- Integrated 5.5-mΩ and 2.0-mΩ Stacked NexFET™ Power Stage
- 500-mV to 1500-mV Reference for Adapative Voltage Scaling (AVS) and Margining through PMBus
- 0.5% Reference Accuracy at 600 mV and Above
- Lossless Low-Side MOSFET Current Sensing
- Voltage Mode Control with Input Feed-Forward
- Differential Remote Sensing
- Monotonic Start-Up into Pre-Biased Output
- Output Voltage and Output Current Reporting
- External Temperature Monitoring with 2N3904 Transistor
- Programmable via the PMBus interface
- VOUT_COMMAND and AVS VOUT Transition Rate
- Overcurrent Protection with Thermal Compensation
- UVLO, Soft-Start and Soft-Stop
- PGOOD, OV, UV, OT Levels
- Fault Responses
- Turn-On and Turn-Off Delays
- Thermal Shutdown
- Pin Strapping for Switching Frequency: 200 kHz to 1 MHz
- Frequency Synchronization to an External Clock
- Footprint Compatible 20-A, 30-A Converters
The TPS544x25 devices are PMBus 1.2 Compliant, non-isolated DC-DC converters with integrated FETs, capable of high-frequency operation and 20-A or 30-A current output from a 5 mm × 7 mm package. High-frequency, low-loss switching, provided by an integrated NexFET™ power stage and optimized drivers, allows for very high-density power solutions. The PMBus interface enables the AVS through VOUT_COMMAND, flexible converter configuration, as well as key parameters monitoring including output voltage, current and an optional external temperature. Response to fault conditions can be set to either restart, latch-off or ignore depending on system requirements.
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Documentación técnica
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Ver todo 9 | Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | TPS544x25 4.5-V to 18-V, 20-A and 30-A SWIFT Synchronous Buck Converters with PMBus and Frequency Synchronization datasheet | PDF | HTML | 15 may 2015 |
| EVM User's guide | TPS5442x5 Step-Down Converter Evaluation Module User's Guide (Rev. B) | PDF | HTML | 26 ago 2021 | |
| Application note | Programming the NVM of PMBus Buck Converters to Support Mass-Production Needs (Rev. B) | 13 may 2019 | ||
| Analog Design Journal | Maximizing power density and thermal performance in power-module designs | 12 dic 2018 | ||
| Application note | Analysis and Design of Input Filter for DC-DC Circuit | 27 nov 2017 | ||
| Application note | SMT Guidelines for Stacked Inductor (Inductor On Top) on Voltage Regulator IC | 22 feb 2016 | ||
| Analog Design Journal | MOSFET power losses and how they affect power-supply efficiency | 26 ene 2016 | ||
| Technical article | Select the correct PMBus POL solution for your application | PDF | HTML | 03 ago 2015 | |
| Application note | Not All Jitter Is Created Equal (Rev. A) | 04 jul 2015 |
Diseño y desarrollo
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
Placa de evaluación
TPS544C25EVM-681 — Módulo de evaluación TPS544C25EVM-681
The TPS544C25EVM-681 evaluation module (EVM) is designed as a single output DC-DC converter that demonstrates a typical low-voltage application while providing a number of test points to evaluate the performance. It uses a nominal 12-V input bus to produce a regulated 0.95-V output at up to (...)
Controlador o biblioteca
PMBUSSW-LINUX — Controlador Linux para PMBUS
The Linux driver supports PMBus controlled Buck Controllers. The Linux driver supports communication through the PMBus and interfaces with the HWMon framework.
Linux Mainline Status
Available in Linux Main line: Yes
Available through git.ti.com: N/A
Supported Devices:
- tps40400
- tps40422
- tps544b20
- tps544b25
- (...)
Diseños de referencia
PMP11399 — Diseño de referencia de sistema de alimentación PMBus para interruptores Ethernet empresariales
PMP11399 is a complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, VTT termination, and auxiliary voltages commonly found on high-performance Ethernet Switches. The hardware is accompanied by a GUI that allows the user to perform real-time configuration and monitoring of the power (...)
Diseños de referencia
PMP12004-HE — Diseño de referencia para la alimentación de un cabezal de radio remoto (RRH) o backhaul (BH) Xilinx
This design for powering Xilinx Zynq UltraScale+ (www.xilinx.com/power) Remote Radio Heads (RRH) features the TPS6508640 and is a small and highly efficient solution. The PMIC reduces size, cost, and power loss by having integrated rails into 1 device, high switching frequency and separate rails (...)
Diseños de referencia
PMP11328 — Diseño de referencia de PMBus de 30 A para el carril central del MPSoC Xilinx Zynq Ultrascale+ ZU9EG
The PMP11328 is a high power density 30A PMBus power supply meeting the Xilinx Ultrascale+ ZU9EG FPGA core rail power specifications for Base Station Remote Radio Unit (RRU) applications. The power supply regulates 0.85V for the core rail at 25A in 55mm x 40mm total power supply PCB area. PMBus (...)
Diseños de referencia
TIDEP0042 — Diseño de referencia de generación de tensión de núcleo AVS SmartReflex para K2E con TPS544C25 y PMB
The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Diseños de referencia
TIDEP0041 — Diseño de referencia de generación de tensión de núcleo AVS SmartReflex, PMBus para K2E
The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Diseños de referencia
PMP10896 — Diseño de referencia de sistema de alimentación PMBus completo para interruptores Ethernet empresari
Complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, and auxiliary voltages found on high-performance Ethernet Switches.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| LQFN-CLIP (RVF) | 40 | Ultra Librarian |
Pedidos y calidad
Información incluida:
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
Información incluida:
- Lugar de fabricación
- Lugar de ensamblaje
Soporte y capacitación
Foros de TI E2E™ con asistencia técnica de los ingenieros de TI
El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.
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