Inicio Gestión de la energía Reguladores lineales y de baja salida (LDO)

TPS74901

ACTIVO

Regulador de tensión de caída ultrabaja ajustable de 3 A y VIN baja (0.8 V) con buena potencia y act

Detalles del producto

Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 20 PSRR at 100 KHz (dB) 28 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 20 PSRR at 100 KHz (dB) 28 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5 x 5 VSON (DRC) 10 9 mm² 3 x 3
  • VOUT range: 0.8V to 3.6V
  • Ultra-low VIN range: 0.8V to 5.5V
  • VBIAS range: 2.7V to 5.5V
  • Low dropout: 120mV (typical) at 3A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 1% (new chip)
  • Accuracy over line, load, and temperature: 2% (legacy chip)
  • Adjustable start-up in-rush control
  • VBIAS permits low VIN operation with good transient response
  • Stable with any output capacitor ≥ 2.2µF
  • Packages:
    • Small, 3mm × 3mm × 1mm VSON
    • 5mm × 5mm × 1mm VQFN and DDPAK-7
  • Active high enable
  • VOUT range: 0.8V to 3.6V
  • Ultra-low VIN range: 0.8V to 5.5V
  • VBIAS range: 2.7V to 5.5V
  • Low dropout: 120mV (typical) at 3A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 1% (new chip)
  • Accuracy over line, load, and temperature: 2% (legacy chip)
  • Adjustable start-up in-rush control
  • VBIAS permits low VIN operation with good transient response
  • Stable with any output capacitor ≥ 2.2µF
  • Packages:
    • Small, 3mm × 3mm × 1mm VSON
    • 5mm × 5mm × 1mm VQFN and DDPAK-7
  • Active high enable

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2µF, and the device is fully specified from –40°C to +125°C. The TPS74901 is offered in a small (3mm × 3mm) VSON package and a small (5mm × 5mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2µF, and the device is fully specified from –40°C to +125°C. The TPS74901 is offered in a small (3mm × 3mm) VSON package and a small (5mm × 5mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

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Documentación técnica

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Tipo Título Fecha
* Data sheet TPS74901 3A, Low Dropout Linear Regulator With Programmable Soft-Start datasheet (Rev. K) PDF | HTML 21 jun 2024
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 ago 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 mar 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 ago 2017
Analog Design Journal Q2 2009 Issue Analog Applications Journal 01 may 2009
Analog Design Journal Taming linear-regulator inrush currents 01 may 2009
EVM User's guide TPS74901EVM-210 (Rev. B) 24 jul 2008
EVM User's guide TPS74901EVM-210 14 abr 2007

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TPS74901EVM-210 — Módulo de evaluación TPS74901 para regulador de tensión ajustable de 3 A y baja VIN (0.8 V) con caíd

El TPS74901EVM-210 facilita la evaluación del CI regulador lineal de caída baja TPS74901.

Estos reguladores requieren una tensión de polarización de baja potencia, VBIAS, y una tensión de entrada de potencia, VIN. El regulador es capaz de proporcionar tensiones de salida de hasta 0,8 V, (...)

Guía del usuario: PDF
Modelo de simulación

TPS74901 PSpice Transient Model (Rev. B)

SLIM031B.ZIP (60 KB) - PSpice Model
Modelo de simulación

TPS74901 TINA-TI Transient Reference Design

SLIM257.TSC (94 KB) - TINA-TI Spice Model
Modelo de simulación

TPS74901 TINA-TI Transient Spice Model

SLIM256.ZIP (35 KB) - TINA-TI Spice Model
Modelo de simulación

TPS74901 Unencrypted PSpice Transient Model

SBVM634.ZIP (3 KB) - PSpice Model
Diseños de referencia

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Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01017 — Diseño de referencia de reloj ADC multicanal de alta velocidad para osciloscopios, comprobadores ina

The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01015 — Diseño de referencia de reloj de 4 GHz para ADC de alta velocidad de 12 bits en osciloscopios digita

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00826 — Diseño de referencia de extremo frontal del osciloscopio de 2 GHz de 50 ohmios

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00432 — Sincronización de ADC de JESD204B Giga-Sample mediante la plataforma Xilinx para sistemas de radar d

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00359 — Diseño de referencia de la solución de registro de tiempo para ADC de GSPS

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TO-263 (KTW) 7 Ultra Librarian
VQFN (RGW) 20 Ultra Librarian
VSON (DRC) 10 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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