Inicio Gestión de la energía Reguladores lineales y de baja salida (LDO)

TPS7A3001-EP

ACTIVO

Regulador LDO, producto mejorado, VIN negativo, 200 mA, nivel de ruido ultrabajo, alta PSRR

Detalles del producto

Output options Adjustable Output Iout (max) (A) 0.2 Vin (max) (V) -3 Vin (min) (V) -36 Vout (max) (V) -1.2 Vout (min) (V) -33 Fixed output options (V) 0 Rating HiRel Enhanced Product Noise (µVrms) 15 PSRR at 100 KHz (dB) 55 Iq (typ) (mA) 0.05 Thermal resistance θJA (°C/W) 69.3 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2.5 Dropout voltage (Vdo) (typ) (mV) 216 Operating temperature range (°C) -55 to 125
Output options Adjustable Output Iout (max) (A) 0.2 Vin (max) (V) -3 Vin (min) (V) -36 Vout (max) (V) -1.2 Vout (min) (V) -33 Fixed output options (V) 0 Rating HiRel Enhanced Product Noise (µVrms) 15 PSRR at 100 KHz (dB) 55 Iq (typ) (mA) 0.05 Thermal resistance θJA (°C/W) 69.3 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2.5 Dropout voltage (Vdo) (typ) (mV) 216 Operating temperature range (°C) -55 to 125
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9
  • Input Voltage Range: –3V to –36V
  • Noise:
    • 14µVRMS (20Hz to 20kHz)
    • 15.1µVRMS (10Hz to 100kHz)
  • Power-Supply Ripple Rejection:
    • 72dB (120Hz)
    • ≥ 55dB (10Hz to 700kHz)
  • Adjustable Output: –1.18V to –35V
  • Maximum Output Current: 200mA
  • Dropout Voltage: 216mV at 100mA
  • Stable with Ceramic Capacitors ≥ 2.2µF
  • CMOS Logic-Level-Compatible Enable Pin
  • Built-In, Fixed, Current-Limit and Thermal Shutdown Protection
  • Available in High Thermal Performance MSOP-8 PowerPAD Package
  • Input Voltage Range: –3V to –36V
  • Noise:
    • 14µVRMS (20Hz to 20kHz)
    • 15.1µVRMS (10Hz to 100kHz)
  • Power-Supply Ripple Rejection:
    • 72dB (120Hz)
    • ≥ 55dB (10Hz to 700kHz)
  • Adjustable Output: –1.18V to –35V
  • Maximum Output Current: 200mA
  • Dropout Voltage: 216mV at 100mA
  • Stable with Ceramic Capacitors ≥ 2.2µF
  • CMOS Logic-Level-Compatible Enable Pin
  • Built-In, Fixed, Current-Limit and Thermal Shutdown Protection
  • Available in High Thermal Performance MSOP-8 PowerPAD Package

The TPS7A3001 is a negative, high-voltage (–36V), ultralow-noise (15.1µVRMS, 72dB PSRR) linear regulator capable of sourcing a maximum load of 200mA.

These linear regulators include a CMOS logic-level-compatible enable pin and capacitor-programmable soft-start function that allows for customized power-management schemes. Other features available include built-in current limit and thermal shutdown protection to safeguard the device and system during fault conditions.

The TPS7A3001 is designed using bipolar technology, and is ideal for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This design makes it an excellent choice to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

In addition, the TPS7A3001 of linear regulators is suitable for post dc/dc converter regulation. By filtering out the output voltage ripple inherent to dc/dc switching conversion, maximum system performance is provided in sensitive instrumentation, test and measurement, audio, and RF applications.

For applications where positive and negative high-performance rails are required, consider TI’s TPS7A49xx family of positive high-voltage, ultralow-noise linear regulators.

The TPS7A3001 is a negative, high-voltage (–36V), ultralow-noise (15.1µVRMS, 72dB PSRR) linear regulator capable of sourcing a maximum load of 200mA.

These linear regulators include a CMOS logic-level-compatible enable pin and capacitor-programmable soft-start function that allows for customized power-management schemes. Other features available include built-in current limit and thermal shutdown protection to safeguard the device and system during fault conditions.

The TPS7A3001 is designed using bipolar technology, and is ideal for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This design makes it an excellent choice to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

In addition, the TPS7A3001 of linear regulators is suitable for post dc/dc converter regulation. By filtering out the output voltage ripple inherent to dc/dc switching conversion, maximum system performance is provided in sensitive instrumentation, test and measurement, audio, and RF applications.

For applications where positive and negative high-performance rails are required, consider TI’s TPS7A49xx family of positive high-voltage, ultralow-noise linear regulators.

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Documentación técnica

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Tipo Título Fecha
* Data sheet Ultra Low Noise Negative Linear Regulator datasheet 20 oct 2011
* VID TPS7A3001-EP VID V6211619 21 jun 2016
* Radiation & reliability report TPS7A3001MDGNTEP Reliability Report 06 feb 2015
White paper Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 14 dic 2022
White paper Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 13 dic 2022
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 jun 2019

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TPS7A30-49EVM-567 — Módulo de evaluación de regulador lineal de tensión de caída baja (LDO) TPS7A3001 y TPS7A4901

The TPS7A30-49EVM-567 is a fully assembled and tested circuit for evaluating the TPS7A3001 and TPS7A4901 low-dropout linear regulators in the DGN (3mm x 5mm MSOP-8) package. The TPS7A30-49EVM-567 includes two independent circuits with outputs of –15 V and +15 V (respectively). These (...)
Guía del usuario: PDF
Modelo de simulación

TPS7A3001 PSpice Transient Model (Rev. A)

SBVM023A.ZIP (50 KB) - PSpice Model
Modelo de simulación

TPS7A3001 TINA-TI Transient Reference Design (Rev. A)

SBVM215A.TSC (107 KB) - TINA-TI Reference Design
Modelo de simulación

TPS7A3001 TINA-TI Transient Spice Model (Rev. A)

SBVM214A.ZIP (13 KB) - TINA-TI Spice Model
Modelo de simulación

TPS7A3001 Unencrypted PSpice Transient Model

SBVM664.ZIP (2 KB) - PSpice Model
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HVSSOP (DGN) 8 Ultra Librarian

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
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  • Monitoreo continuo de confiabilidad
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