The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to
160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to
support demanding, high input frequency signals with large dynamic range requirements. A clock
input divider allows more flexibility for system clock architecture design and the SYSREF input
enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order
to reduce the number of interface lines, thus allowing high system integration density. The
JESD204B interface is a serial interface, where the data of each ADC are serialized and output over
only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC
sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each
channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to
160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to
support demanding, high input frequency signals with large dynamic range requirements. A clock
input divider allows more flexibility for system clock architecture design and the SYSREF input
enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order
to reduce the number of interface lines, thus allowing high system integration density. The
JESD204B interface is a serial interface, where the data of each ADC are serialized and output over
only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC
sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each
channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.