The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface datasheet (Rev. B) | PDF | HTML | 2014/05/06 |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 2017/09/27 | ||
| EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 2016/04/28 | ||
| EVM User's guide | TSW3XJ8XEVM User's Guide (Rev. B) | 2016/03/09 | ||
| Analog Design Journal | JESD204B over optical fiber enables new architecture for phased-array radar | 2016/01/26 | ||
| Application note | System solution for avionics & defense | 2015/09/23 | ||
| White paper | Ready to make the jump to JESD204B? White Paper (Rev. B) | 2015/03/19 | ||
| EVM User's guide | Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) | 2014/09/15 | ||
| Design guide | Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) | 2013/08/14 | ||
| Application note | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012/10/23 |
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DAC3XJ8XEVM은 고속 JESD204B 인터페이스(DAC37J82, DAC37J84, DAC38J82, DAC38J84)로 이루어진 DAC DAC3XJ8X 제품군 평가용으로 설계된 평가 모듈(EVM)입니다. 이 EVM에는 온보드 클로킹 솔루션(LMK04828), 변압기 연결 출력부, 전체 전력 솔루션, 사용이 간편한 소프트웨어 GUI 및 USB 인터페이스가 포함되어 있습니다.
DAC3XJ8XEVM은 고속 데이터 컨버터 평가를 위해 고속 데이터 컨버터 프로(HSDCPro) 소프트웨어를 통해 텍사스 인스트루먼트의 JESD204B (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
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