TCA9517A
- Two-Channel Bidirectional Buffer
- I2C Bus and SMBus Compatible
- Operating Supply Voltage Range of 0.9V to 5.5V on A-side
- Operating Supply Voltage Range of 2.7V to 5.5V on B-side
- Voltage-Level Translation From 0.9V - 5.5V to 2.7V - 5.5V
- Footprint and Functional Replacement for PCA9515B
- Active-High Repeater-Enable Input
- Open-Drain I2C I/O
- 5.5V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation
- Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters
- High-Impedance I2C Pins When Powered-Off
- Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 5500V Human-Body Model (A114-A)
- 200V Machine Model (A115-A)
- 1000V Charged-Device Model (C101)
The TCA9517A is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It provides bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9V) and higher voltages (2.7V to 5.5V) in mixed-mode applications. This device enables I2C and SMBus systems to be extended without degradation of performance, even during level shifting.
The TCA9517A buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of up to 400pF bus capacitance to be connected in an I2C application.
The TCA9517A has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage tolerant to 5.5V, even when the device is unpowered (VCCB and/or VCCA = 0V).
The TCA9517A offers a higher contention level threshold, VILC, than the TCA9517, which allows connections to slaves which have weaker pulldown ability.
The type of buffer design on the B-side prevents it from being used in series with devices which use static voltage offset. This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.
The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TCA9517A Level-Shifting I2 C Bus Repeater datasheet (Rev. D) | PDF | HTML | 2024年 9月 5日 |
Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
Application note | Resolving Improper Implementation of the Static Voltage Offset on I2C Buffers | PDF | HTML | 2023年 10月 9日 | |
Application note | Why, When, and How to use I2C Buffers | 2018年 5月 23日 | ||
Application note | Choosing the Correct I2C Device for New Designs | PDF | HTML | 2016年 9月 7日 | |
Application note | Understanding the I2C Bus | PDF | HTML | 2015年 6月 30日 | |
Application note | Maximum Clock Frequency of I2C Bus Using Repeaters | 2015年 5月 15日 | ||
Application note | I2C Bus Pull-Up Resistor Calculation | PDF | HTML | 2015年 2月 13日 |
設計與開發
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I2C-DESIGNER — I2C 設計工具
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TINA-TI — 基於 SPICE 的類比模擬程式
PMP23365 — 具備外部熱插拔及遙測功能的 24V、3A 8 類 PoE PD 參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。