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UCC27624-Q1

現行

具 4V UVLO、30V VDD 和低傳播延遲的車用 5A/5A 雙通道閘極驅動器

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產品詳細資料

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 26 Features Enable pin Operating temperature range (°C) -40 to 150 Rise time (ns) 6 Fall time (ns) 10 Propagation delay time (µs) 0.017 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -10 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 26 Features Enable pin Operating temperature range (°C) -40 to 150 Rise time (ns) 6 Fall time (ns) 10 Propagation delay time (µs) 0.017 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -10 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6 WSON (DSD) 8 9 mm² 3 x 3
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H1C
    • Device CDM ESD Classification Level C6
  • Typical 5A peak source and sink drive current for each channel
  • Input and enable pins capable of handling –10V
  • Output capable of handling –2V transients
  • Absolute maximum VDD voltage: 30V
  • Wide VDD operating range from 4.5V to 26V with UVLO
  • Hysteretic-logic thresholds for high noise immunity
  • VDD independent input thresholds (TTL compatible)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between the two channels
  • Two channels can be paralleled for higher drive current
  • SOIC8 and VSSOP8 PowerPAD™ package options
  • Operating junction temperature range of –40°C to 150°C
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H1C
    • Device CDM ESD Classification Level C6
  • Typical 5A peak source and sink drive current for each channel
  • Input and enable pins capable of handling –10V
  • Output capable of handling –2V transients
  • Absolute maximum VDD voltage: 30V
  • Wide VDD operating range from 4.5V to 26V with UVLO
  • Hysteretic-logic thresholds for high noise immunity
  • VDD independent input thresholds (TTL compatible)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between the two channels
  • Two channels can be paralleled for higher drive current
  • SOIC8 and VSSOP8 PowerPAD™ package options
  • Operating junction temperature range of –40°C to 150°C

The UCC27624-Q1 is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET, IGBT, SiC, and GaN power switches. UCC27624-Q1 has a typical peak drive strength of 5A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The device’s fast propagation delay (17ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.

UCC27624-Q1 can handle –10V at its inputs, which improves robustness in systems with moderate ground bouncing. The inputs are independent of supply voltage and can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The device’s transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.

The UCC27624-Q1 also features undervoltage lockout (UVLO) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.

The UCC27624-Q1 is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET, IGBT, SiC, and GaN power switches. UCC27624-Q1 has a typical peak drive strength of 5A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The device’s fast propagation delay (17ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.

UCC27624-Q1 can handle –10V at its inputs, which improves robustness in systems with moderate ground bouncing. The inputs are independent of supply voltage and can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The device’s transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.

The UCC27624-Q1 also features undervoltage lockout (UVLO) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.

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類型 標題 日期
* Data sheet UCC27624-Q1 30V, 5A, Dual-Channel, Low-Side Gate Driver with –10V Input Capability For Automotive Applications datasheet (Rev. C) PDF | HTML 2024年 5月 30日
Application note Selecting Gate Drivers for HVAC Systems PDF | HTML 2024年 4月 4日
Application note Why use a Gate Drive Transformer? PDF | HTML 2024年 3月 4日
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 2024年 1月 22日
Application note Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 2024年 1月 22日
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 2021年 11月 10日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application note Improving Efficiency of DC-DC Conversion through Layout 2019年 5月 7日
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 2019年 1月 18日
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 2018年 11月 26日
Application note PFC Design Choice for On Board Charger Designs 2018年 5月 24日
Application brief Reducing Switching Losses in On-Board Chargers for Electric Vehicles 2018年 3月 27日
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 2018年 3月 16日

設計與開發

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開發板

UCC27624DGNEVM — 適用雙通道 30-V、5-A 高速低壓側閘極驅動器的 UCC27624 評估模組

UCC27624 評估模組 (EVM) 專為評估 30-V、5-A 單通道閘極驅動器而設計。此 EVM 的目標是依產品規格書參數評估驅動器 IC。驅動器 IC 可針對各種電容與電阻負載進行評估。EVM 可設定為平行處理驅動器 IC 通道,以獲得更高的閘極驅動器輸出電流。EVM 具備評估 TO-220 體積功率電晶體的佈建。

使用指南: PDF
開發板

UCC27624EVM — UCC27624 評估模組雙通道 30-V、5-A 高速低壓側閘極驅動器

UCC27624 評估模組 (EVM) 專為評估 TI 的 30-V、5-A 單通道閘極驅動器而設計。此 EVM 的目標是依產品規格書參數評估驅動器 IC。驅動器 IC 可針對各種電容與電阻負載進行評估。EVM 可設定為平行處理驅動器 IC 通道,以獲得更高的閘極驅動器輸出電流。EVM 具備評估 TO-220 體積功率電晶體的佈建。

使用指南: PDF | HTML
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模擬型號

UCC27624 PSpice Transient Model

SLUM884.ZIP (32 KB) - PSpice Model
模擬型號

UCC27624 SIMPLIS Model

SLUM795.ZIP (34 KB) - SIMPLIS Model
計算工具

SLURB19 UCC27624-Q1 Schematic Review Template

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產品
低壓側驅動器
UCC27624-Q1 具 4V UVLO、30V VDD 和低傳播延遲的車用 5A/5A 雙通道閘極驅動器
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HVSSOP (DGN) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
WSON (DSD) 8 Ultra Librarian

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