計算工具
UCC5350
- Feature options
- Split outputs (UCC53x0S)
- UVLO referenced to GND2 (UCC53x0E)
- Miller clamp option (UCC53x0M)
- 8-pin D (4mm creepage) and DWV (8.5mm creepage) package
- 60ns (typical) propagation delay
- 100kV/µs minimum CMTI
- Isolation barrier life > 40 Years
- 3V to 15V input supply voltage
- Up to 33V driver supply voltage
- 8V and 12V UVLO options
- Negative 5V handling capability on input pins
- Safety-related certifications:
- 7000VPK isolation DWV (planned) and 4242VPK isolation D per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 5000VRMS DWV and 3000VRMS D isolation rating for 1 minute per UL 1577
- CQC certification per GB4943.1-2011 D and DWV (planned)
- CMOS inputs
- Operating temperature: –40°C to +125°C
The UCC53x0 is a family of single-channel, isolated gate drivers designed to drive MOSFETs, IGBTs, SiC MOSFETs, and GaN FETs (UCC5350SBD). The UCC53x0S provides a split output that controls the rise and fall times individually. The UCC53x0M connects the gate of the transistor to an internal clamp to prevent false turn-on caused by Miller current. The UCC53x0E has its UVLO2 referenced to GND2 to get a true UVLO reading.
The UCC53x0 is available in a 4mm SOIC-8 (D) or 8.5mm SOIC-8 (DWV) package and can support isolation voltage up to 3kVRMS and 5kVRMS, respectively. With these various options the UCC53x0 family is a good fit for motor drives and industrial power supplies.
Compared to an optocoupler, the UCC53x0 family has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.
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開發板
UCC5320SCEVM-058 — UCC5320SC 隔離式閘極驅動器評估模組
UCC5320SCEVM is an Evaluation Module used to evaluate UCC53xx family of devices and it provides user with flexiblity of configuring driver to Split output, miller clamp or UVLO based on the device used . The EVM features enough test points & jumper options for one to evaluate the device (...)
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
PMP23126 — 3-kW 全橋相移式轉換器搭配主動箝位參考設計，可提供 > 270-W/in3 的功率密度
此參考設計是專為最高功率密度設計的 GaN 式 3-kW 全橋相移式轉換器 (PSFB)。此設計具主動箝位可減少二次側同步整流器 MOSFET 的電壓應力，以使用具更出色品質因數 (FoM) 的低電壓額定值 MOSFET。PMP23126 使用我們的一次側 30mΩ GaN 和二次側矽 MOSFET。與矽 MOSFET 相比，具整合式驅動器與保護的 LMG3522 頂端冷卻 GaN 可在更大的操作範圍中維持 ZVS，以實現更高效率。PSFB 可在 100 kHz 運作，並可達 97.74% 峰值效率。
Test report: PDF
參考設計
TIDA-01599 — TÜV SÜD 評估工業驅動器的安全扭矩關閉 (STO) 參考設計 (IEC 61800-5-2)
本參考設計概述具有 CMOS 輸入隔離式 IGBT 閘極驅動器的三相逆變器的安全扭矩關閉 (STO) 子系統。STO 子系統採用雙通道架構 (1oo2)，硬體容錯範圍爲 1 (HFT=1)。實作時遵循去能脫扣概念。當雙 STO 輸入 (STO_1 和 STO_2) 變低電位作動時，六個隔離 IGBT 柵極驅動器的一次和二次側對應電源供電將透過負載開關切斷。如此可消除控制馬達並為馬達通電的可能性。STO 參考設計 (1oo2) 已由 TÜV SÜD 進行評估，一般適用於 SIL 3 和 PL e/Cat。3.
參考設計
TIDA-01420 — 適用於工業驅動器的基本隔離式三相精巧型功率級參考設計
This three-phase, compact power stage reference design for industrial drives, which uses a UCC53xx gate driver to support basic capacitive isolation requirements, provides an increased lifespan and better propagation delay match over optocouplers to minimize inverter deadband distortions and (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| SOIC (DWV) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。