UCC27532-Q1
Controlador de puerta monocanal de 2.5 A/5 A con UVLO de 8 V, VDD de 35 V y entradas CMOS para autom
UCC27532-Q1
- Qualified for automotive applications
- AEC-Q100 qualified with the following results:
- Device temperature grade 1
- Low-cost gate driver (offering optimal solution for driving FET and IGBTs)
- Superior replacement to discrete transistor pair drive (providing easy interface with controller)
- CMOS compatible input-logic threshold (becomes fixed at VDD above 18V)
- Split outputs allow separate turnon and turnoff tuning
- Enable with Fixed TTL compatible threshold
- High 2.5A source and 5A sink peak-drive currents at 18V VDD
- Wide VDD range from 10V up to 35V
- Input pins capable of withstanding up to –5V DC below ground
- Output held low when inputs are floating or during VDD UVLO
- Fast propagation delays (17ns typical)
- Fast rise and fall times (15ns and 7ns typical with 1800pF load)
- Undervoltage lockout (UVLO)
- Used as a high-side or low-side driver (if designed with proper bias and signal isolation)
- Low-cost space-saving 6-pin DBV (SOT-23) package
- Operating temperature range of –40°C to 140°C
The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5A source and 5A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.
The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17ns (typically).
The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18V. When VDD is above 18V, the input threshold remains fixed at the maximum level.
The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and .
Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.
The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.
Documentación técnica
Diseño y desarrollo
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PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI
Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
---|---|---|
SOT-23 (DBV) | 6 | Ultra Librarian |
Pedidos y calidad
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
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- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
- Lugar de fabricación
- Lugar de ensamblaje
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