The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed
forward channel and a bidirectional control channel for data transmission over a single
differential pair. The Serializer/Deserializer pair is targeted for direct connections between
automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport
sends 16 bits of image data over a single high-speed serial stream together with a low latency
bidirectional control channel transport that supports I2C. Included with
the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to
monitor transmission link errors. Using TI’s embedded clock technology allows transparent
full-duplex communication over a single differential pair, carrying asymmetrical bidirectional
control information without the dependency of video blanking intervals. This single serial stream
simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems
between parallel data and clock paths. This significantly saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss
from the media over longer distances. Internal DC balanced encoding/decoding is used to support
AC-Coupled interconnects.
A Serializer standby function provides a low power-savings mode with a remote wake up
capability for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is
offered in a 40-pin WQFN (6mm x 6mm) package.
The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed
forward channel and a bidirectional control channel for data transmission over a single
differential pair. The Serializer/Deserializer pair is targeted for direct connections between
automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport
sends 16 bits of image data over a single high-speed serial stream together with a low latency
bidirectional control channel transport that supports I2C. Included with
the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to
monitor transmission link errors. Using TI’s embedded clock technology allows transparent
full-duplex communication over a single differential pair, carrying asymmetrical bidirectional
control information without the dependency of video blanking intervals. This single serial stream
simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems
between parallel data and clock paths. This significantly saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss
from the media over longer distances. Internal DC balanced encoding/decoding is used to support
AC-Coupled interconnects.
A Serializer standby function provides a low power-savings mode with a remote wake up
capability for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is
offered in a 40-pin WQFN (6mm x 6mm) package.