The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1
deserializer, provides a solution for secure distribution of content-protected digital video within
automotive entertainment systems. This chipset translates a FPD-Link video interface into a
single-pair high-speed serialized interface. The digital video data is protected using the industry
standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III
serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed
back channel communication over a single differential link. Consolidation of audio, video, and
control data over a single differential pair reduces the interconnect size and weight, while also
eliminating skew issues and simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and
level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are
serialized along with three video control signals, and up to four I2S
data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also
minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage
differential signaling, data scrambling and randomization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys
are stored in on-chip memory.
The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1
deserializer, provides a solution for secure distribution of content-protected digital video within
automotive entertainment systems. This chipset translates a FPD-Link video interface into a
single-pair high-speed serialized interface. The digital video data is protected using the industry
standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III
serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed
back channel communication over a single differential link. Consolidation of audio, video, and
control data over a single differential pair reduces the interconnect size and weight, while also
eliminating skew issues and simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and
level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are
serialized along with three video control signals, and up to four I2S
data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also
minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage
differential signaling, data scrambling and randomization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys
are stored in on-chip memory.