The DS90UH928Q-Q1 deserializer, in conjunction with a
DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution
for secure distribution of content-protected digital video and audio within automotive infotainment
systems. The device converts a high-speed serialized interface with an embedded clock, delivered
over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair
(OpenLDI (FPD-Link)), and I2S audio data. The digital video
and audio data is protected using the industry standard HDCP copy protection scheme.The
serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and
low-speed full duplex back channel communication over a single differential link. Consolidation of
audio, video data and control over a single differential pair reduces the interconnect size and
weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for
transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage
differential signaling.
The HDCP cipher engine is implemented in both the serializer and
deserializer. HDCP keys are stored in on-chip memory.
The DS90UH928Q-Q1 deserializer, in conjunction with a
DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution
for secure distribution of content-protected digital video and audio within automotive infotainment
systems. The device converts a high-speed serialized interface with an embedded clock, delivered
over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair
(OpenLDI (FPD-Link)), and I2S audio data. The digital video
and audio data is protected using the industry standard HDCP copy protection scheme.The
serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and
low-speed full duplex back channel communication over a single differential link. Consolidation of
audio, video data and control over a single differential pair reduces the interconnect size and
weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for
transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage
differential signaling.
The HDCP cipher engine is implemented in both the serializer and
deserializer. HDCP keys are stored in on-chip memory.