The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer,
provides a complete digital interface for concurrent transmission of high-speed video, audio, and
control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video-display systems with HD formats and
automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded
bidirectional control channel and low latency GPIO controls. This chipset translates a parallel
interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III,
supports full duplex of high-speed video data transmission and bidirectional control communication
over a single differential link. Consolidation of video data and control over a single differential
pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying
system design.
The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data
payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24
data bits are serialized along the video control signals.
Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by
the use of low voltage differential signaling, data scrambling and randomization and spread
spectrum clocking compatibility.
The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer,
provides a complete digital interface for concurrent transmission of high-speed video, audio, and
control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video-display systems with HD formats and
automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded
bidirectional control channel and low latency GPIO controls. This chipset translates a parallel
interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III,
supports full duplex of high-speed video data transmission and bidirectional control communication
over a single differential link. Consolidation of video data and control over a single differential
pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying
system design.
The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data
payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24
data bits are serialized along the video control signals.
Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by
the use of low voltage differential signaling, data scrambling and randomization and spread
spectrum clocking compatibility.