LMK61E2EVM
LMK61E2EVM 超低ジッタ、プログラマブル・オシレータ評価モジュール
LMK61E2EVM
概要
The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.
The LMK61E2EVM can be used as a high performance clock source for jitter criticial applications and can easily be customized to any user desired frequency and output format. The onboard USB to I2C interface allows for device configuration via a software graphical user interface (GUI) and requires no external input or power for device operation. The edge-launch SMA ports provide access to the LMK61E2’s differential clock output for interfacing to test equipment or reference boards using commercially available coaxial cables, adapters, or baluns (not included).
特長
- Ultra low jitter differential clock generation
- Powered over USB or externally (SMA connector)
- Onboard USB to I2C interface
- Coarse and Fine Frequency margining
- GUI platform for full access to LMK03328 registers and EEPROM
- LMK61E2EVM
- 3-ft. USB cable, Q362-ND
購入と開発の開始
LMK61E2EVM — LMK61E2EVM 超低ジッタ、プログラマブル・オシレータ評価モジュール
SNAC074 — LMK61xx Oscillator Programming Tool
SNAC074 — LMK61xx Oscillator Programming Tool
製品
発振器
ハードウェア開発
評価ボード
リリース情報
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.6 installer binary for Windows operating system
製品
クロック・ジェネレータ
RF PLL / シンセサイザ
クロック・バッファ
発振器
クロック ジッタ クリーナ
クロック ネットワーク シンクロナイザ
ハードウェア開発
評価ボード
ドキュメント
TICS Pro 1.7.7.6 Release Notes
TICS Pro 1.7.7.6 Software Manifest
リリース情報
Added Features
LMK5Bxxyyy, LMK5Cxxyyy
- Warnings and errors improved, particularly corrective suggestions
- REFx_FREQ=0 automatically disables DPLL reference input selection for that input
- Input validation enabled and disabled by start page settings, including 1PPS
- APLL reference selection moved to Step 5, just before clock output definition
- Quick-set multiple outputs to the same settings on frequency planner
- BAW VCO allows some ppm deviation
- Force SYSREF option on OUT0/1
- Expose DPLLx_LCK_TIMER field
- Match LMK05318B EEPROM page design
- .EPR export option
- EEPROM SRAM programming generation support
- For complete changelist, see release notes
LMK3H0102
- Configuration search tool
- Wizard: voltage selection option
Bug Fixes
- LMK04832-SP, LMK04832-SEP, LMK04714-Q1, LMK04368-EP - PD_FIN0 corrected to FIN0_PD
- LMK3H0102 - Several wizard bugfixes
Known Issues
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技術資料
種類 | タイトル | 英語版のダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | EVM ユーザー ガイド (英語) | LMK61E2EVM, LMK61E0MEVM User's Guide (Rev. B) | 2017年 8月 10日 | |||
証明書 | LMK61E2EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
データシート | LMK61E2 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM データシート (Rev. B) | PDF | HTML | 2017年 2月 3日 | |||
技術記事 | How to select an optimal clocking solution for your FPGA-based design | PDF | HTML | 2015年 12月 9日 |