Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL

DS91C180

ACTIVO

Par de controlador/receptor de línea M-LVDS de 100 MHz

Detalles del producto

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6
  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

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Documentación técnica

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Tipo Título Fecha
* Data sheet DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair datasheet (Rev. M) 18 abr 2013
Application brief How Far, How Fast Can You Operate MLVDS? 06 ago 2018
Application note Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) 26 abr 2013
Application note Introduction to M-LVDS (TIA/EIA-899) (Rev. A) 03 ene 2013

Diseño y desarrollo

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Modelo de simulación

DS91C180 IBIS Model

SNLM029.ZIP (15 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 14 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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