DS99R106
Deserializador LVDS de 3 MHz a 40 MHz y 24 bits con equilibrio DC
DS99R106
- 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
- Capable to Drive Shielded Twisted-Pair Cable
- User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
- Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
- Individual Power-Down Controls for Both Transmitter and Receiver
- Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
- All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
- LOCK Output Flag to Ensure Data Integrity at Receiver Side
- Balanced TSETUP/THOLD between RCLK and RDATA on Receiver Side
- PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
- All LVCMOS Inputs and Control Pins have Internal Pulldown
- On-Chip Filters for PLLs on Transmitter and Receiver
- Integrated 100Ω Input Termination on Receiver
- 4 mA Receiver Output Drive
- 48-Pin TQFP and 48-Pin WQFN Packages
- Pure CMOS .35 μm Process
- Power Supply Range 3.3V ± 10%
- Temperature Range 0°C to +70°C
- 8 kV HBM ESD Tolerance
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The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
Documentación técnica
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D) | 16 abr 2013 |
Pedidos y calidad
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
- Lugar de fabricación
- Lugar de ensamblaje