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Circuitos integrados LVDS, M-LVDS y PECL

SN65CML100

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Traductor/repetidor LVDS/LVPECL/CML a CML de 1.5 Gbps

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SN65CML100

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Detalles del producto

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet 1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater datasheet 11 nov 2002
Application note Signaling Rate vs. Distance for Differential Buffers 26 ene 2010
EVM User's guide 2-GBPS Differential Repeater EVM (Rev. A) 11 nov 2002

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

SN65CML100EVM — SN65CML100 Módulo de evaluación

The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)

Guía del usuario: PDF
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Modelo de simulación

SN65CML100 IBIS Model

SLLC131.ZIP (3 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
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Pedidos y calidad

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  • Marcado del dispositivo
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  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
  • Lugar de ensamblaje

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