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Circuitos integrados HDMI, DisplayPort y MIPI

SN65DSI85

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MIPI® DSI de doble canal a puente LVDS Flatlink™ de doble enlace

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SN65DSI85

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Detalles del producto

Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 8 Number of channels 2 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 8 Number of channels 2 Supply voltage (V) 1.8 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps WQXGA 2560 × 1600 resolution at 18-bpp and 24-bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI® front-end configurable for single-channel or dual-channel DSI configurations
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
  • Supports two single-channel DSI to two single-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low-power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI® ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS pin order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm x 5 mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps WQXGA 2560 × 1600 resolution at 18-bpp and 24-bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI® front-end configurable for single-channel or dual-channel DSI configurations
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
  • Supports two single-channel DSI to two single-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low-power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI® ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS pin order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm x 5 mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65DSI85 MIPI® DSI Bridge to FlatLink LVDS Dual Channel DSI to Dual-Link LVDS datasheet (Rev. G) 01 oct 2020
Application note Troubleshooting SN65DSI8x - Tips and Tricks 27 ago 2018
EVM User's guide SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide 17 nov 2015
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) 11 abr 2013
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) 08 abr 2013

Diseño y desarrollo

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Placa de evaluación

SN65DSI85EVM — SN65DSI85 Módulo de evaluación de MIPI® DSI de doble canal a puente LVDS FlatLink™ de doble enlace

The SN65DSI85EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implementthe SN65DSI85 device in system hardware. This EVM can be used as a hardware reference design for any implementation using the SN65DSI85 device. The SN65DSI85EVM includes (...)
Guía del usuario: PDF
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Modelo de simulación

SN65DSI85 Hspice Model

SLLJ007.ZIP (1092 KB) - HSpice Model
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Modelo de simulación

SN65DSI85 IBIS Model (Rev. A)

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
NFBGA (ZXH) 64 Ultra Librarian
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Pedidos y calidad

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  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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