Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL
Inicio
Interfaz
Circuitos integrados LVDS, M-LVDS y PECL

SN65LVDM051

ACTIVO

Transmisor y receptor LVDS doble

Haga su pedido ahora
Hoja de datos

SN65LVDM051

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Function Transceiver Protocols LVDM, LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVDM, LVDS, LVTTL Output signal LVDM, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols LVDM, LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVDM, LVDS, LVTTL Output signal LVDM, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Low-Voltage Differential 50- Line Drivers and Receivers
  • Typical Full-Duplex Signaling Rates of 100 Mbps
  • Bus-Terminal ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 340 mV With a 50- Load
  • Valid Output With as Little as 50-mV Input
    Voltage Difference
  • Propagation Delay Times
    • Driver: 1.7 ns Typical
    • Receiver: 3.7 ns Typical
  • Power Dissipation at 200 MHz
    • Driver: 50 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Driver Is High Impedance When Disabled or With VCC < 1.5 V
  • Receiver Has Open-Circuit Failsafe
  • Low-Voltage Differential 50- Line Drivers and Receivers
  • Typical Full-Duplex Signaling Rates of 100 Mbps
  • Bus-Terminal ESD Exceeds 12 kV
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 340 mV With a 50- Load
  • Valid Output With as Little as 50-mV Input
    Voltage Difference
  • Propagation Delay Times
    • Driver: 1.7 ns Typical
    • Receiver: 3.7 ns Typical
  • Power Dissipation at 200 MHz
    • Driver: 50 mW Typical
    • Receiver: 60 mW Typical
  • LVTTL Input Levels Are 5-V Tolerant
  • Driver Is High Impedance When Disabled or With VCC < 1.5 V
  • Receiver Has Open-Circuit Failsafe

The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50- load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100 characteristic impedance.

The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics.

The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are characterized for operation from –40°C to 85°C.

The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50- load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100 characteristic impedance.

The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics.

The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are characterized for operation from –40°C to 85°C.
filter Buscar otro/a Circuitos integrados LVDS, M-LVDS y PECL
Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Pin por pin con la misma funcionalidad que el dispositivo comparado
SN65LVDM051-Q1 ACTIVO Controladores y receptores de línea diferencial de alta velocidad en catálogo automotriz Automotive grade with temperature range from –40°C to +125°C

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 4
Tipo Título Fecha
* Data sheet High-Speed Differential Line Drivers And Receivers datasheet (Rev. J) 17 jul 2009
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 22 jun 2023
Application brief How Far, How Fast Can You Operate MLVDS? 06 ago 2018
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 20 nov 2001

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDM051 IBIS Model

SLLM010.ZIP (51 KB) - IBIS Model
Descargar
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Solicitar
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
View Options
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos