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SN65LVDS101

ACTIVO

Traductor y repetidor LVDS, LVPECL y CML a búfer LVPECL de 2 Gbps

Detalles del producto

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2000 Input signal CML, LVDS, LVPECL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2000 Input signal CML, LVDS, LVPECL Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65LVDx10x Differential Translator/Repeater datasheet (Rev. E) PDF | HTML 20 jul 2015
Application note Signaling Rate vs. Distance for Differential Buffers 26 ene 2010
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 oct 2007
Application note DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 19 feb 2003
EVM User's guide 2-GBPS Differential Repeater EVM (Rev. A) 11 nov 2002
More literature HPL EVM Program 29 ago 2002
EVM User's guide 2-GBPS Differential Repeater EVM 08 ago 2002

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

SN65CML100EVM — SN65CML100 Módulo de evaluación

The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)

Guía del usuario: PDF
Placa de evaluación

SN65LVDS101EVM — SN65LVDS101 Módulo de evaluación

The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to (...)

Guía del usuario: PDF
Modelo de simulación

SN65LVDS101 IBIS Model (Rev. A)

SLLC125A.ZIP (6 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-01378 — Diseño de referencia de receptor de banda ancha para aplicaciones DOCSIS 3.1 del cliente al servidor

This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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