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SN65LVDS31

ACTIVO

Controlador diferencial LVDS cuádruple de 400 Mbps y alta velocidad

Detalles del producto

Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load
  • Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps)
  • Typical Propagation Delay Times of 1.7 ns
  • Operate From a Single 3.3-V Supply
  • Power Dissipation 25 mW Typical Per Driver at 200 MHz
  • Driver at High-Impedance When Disabled or With VCC = 0
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels
  • Pin Compatible With AM26LS31, MC3487, and µA9638
  • Cold Sparing for Space and High-Reliability Applications Requiring Redundancy
  • Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load
  • Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps)
  • Typical Propagation Delay Times of 1.7 ns
  • Operate From a Single 3.3-V Supply
  • Power Dissipation 25 mW Typical Per Driver at 200 MHz
  • Driver at High-Impedance When Disabled or With VCC = 0
  • Bus-Terminal ESD Protection Exceeds 8 kV
  • Low-Voltage TTL (LVTTL) Logic Input Levels
  • Pin Compatible With AM26LS31, MC3487, and µA9638
  • Cold Sparing for Space and High-Reliability Applications Requiring Redundancy

The SN55LVDS31, SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 devices are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

The SN55LVDS31, SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 devices are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SNx5LVDSxx High-Speed Differential Line Drivers datasheet (Rev. N) PDF | HTML 21 ene 2021
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter 28 dic 2018
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application note LVDS Multidrop Connections (Rev. A) 11 feb 2002
Application note Performance of LVDS with Different Cables (Rev. B) 11 feb 2002
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

SN65LVDS31-32BEVM — SN65LVDS31-32B Módulo de evaluación de señalización diferencial de baja tensión para LVDS31 y LVDS32

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

Combination Table

As seen (...)

Guía del usuario: PDF
Placa de evaluación

SN65LVDS31-32EVM — Módulo de evaluación SN65LVDS31-32EVM para SNx5LVDS31 y SNx5LVDS32

The SN65LVDS31-32EVM evaluation moduel (EVM) includes the SV65LVDS31 quad driver and the SN65LVDS32 quad receiver. The SN65LVDS31 device is a TIA/EIA-644 standard-compliant LVDS driver. The SN65LVDS32 device is a TIA/EIA-644 standard-compliant receiver that has a passive open-circuit failsafe (...)

Guía del usuario: PDF
Placa de evaluación

SN65LVDS31-33EVM — Módulo de evaluación para SN65LVDS31 y SN65LVDS33

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

As seen in the Combination (...)

Guía del usuario: PDF
Modelo de simulación

SN65LVDS31 IBIS Model (Rev. B)

SLLC012B.ZIP (6 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-060017 — Diseño de referencia de transmisión de señales SPI a través de la interfaz LVDS

This reference design demonstrates how to resolve and optimize signal integrity challenges typically found when sending SPI signals over longer distance on the same PCB or off PCB to another board in a noisy environment by transmitting SPI signals over an LVDS interface. The concept offers (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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