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SN65LVDT125A

ACTIVO

Interruptor de conexión cruzada LVDS de 4x4 y 1.5 Gbps

Detalles del producto

Function Crosspoint Protocols CML, LVDS, LVPECL Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Crosspoint Protocols CML, LVDS, LVPECL Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DBT) 38 62.08 mm² 9.7 x 6.4
  • Signaling Rates >1.5 Gbps per Channel
  • Supports Telecom/Datacom and HDTV
    Video Switching
  • Non-Blocking Architecture Allows Each
    Output to be Connected to Any Input
  • Compatible With ANSI TIA/EIA-644-A LVDS
    Standard
  • 25 mV of Input Voltage Threshold Hysteresis
  • Propagation Delay Times, 900 ps Typical
  • Inputs Electrically Compatible With LVPECL,
    CML and LVDS Signal Levels
  • Operates From a Single 3.3-V Supply
  • Integrated 110-Ω Line Termination Resistors
    Available With SN65LVDT125A
  • APPLICATIONS
    • Clock Buffering/Clock Muxing
    • Wireless Base Stations
    • High-Speed Network Routing
    • HDTV Video Switching

  • Signaling Rates >1.5 Gbps per Channel
  • Supports Telecom/Datacom and HDTV
    Video Switching
  • Non-Blocking Architecture Allows Each
    Output to be Connected to Any Input
  • Compatible With ANSI TIA/EIA-644-A LVDS
    Standard
  • 25 mV of Input Voltage Threshold Hysteresis
  • Propagation Delay Times, 900 ps Typical
  • Inputs Electrically Compatible With LVPECL,
    CML and LVDS Signal Levels
  • Operates From a Single 3.3-V Supply
  • Integrated 110-Ω Line Termination Resistors
    Available With SN65LVDT125A
  • APPLICATIONS
    • Clock Buffering/Clock Muxing
    • Wireless Base Stations
    • High-Speed Network Routing
    • HDTV Video Switching

The SN65LVDS125A and SN65LVDT125A are 4x4 nonblocking crosspoint switches. Low-voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT125A incorporates 110-Ω termination resistors for those applications where board space is a premium.

Designed to support signaling rates up to 1.5 Gbps for OC-12 clocks (622 MHz). The 1.5-Gbps signaling rate allows use in HDTV systems, including SMPTE 292 video applications requiring signaling rates of 1.485 Gbps.

The SN65LVDS125A and SN65LVDT125A are characterized for operation from –40°C to 85°C.

The SN65LVDS125A and SN65LVDT125A are 4x4 nonblocking crosspoint switches. Low-voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT125A incorporates 110-Ω termination resistors for those applications where board space is a premium.

Designed to support signaling rates up to 1.5 Gbps for OC-12 clocks (622 MHz). The 1.5-Gbps signaling rate allows use in HDTV systems, including SMPTE 292 video applications requiring signaling rates of 1.485 Gbps.

The SN65LVDS125A and SN65LVDT125A are characterized for operation from –40°C to 85°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65LVDS125A, SN65LVDT125A - LVDS 4x4 Crosspoint Switch datasheet (Rev. C) 27 jun 2011
EVM User's guide 4x4 Crosspoint Switch EVM User's Guide (Rev. A) 29 ene 2004

Diseño y desarrollo

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Modelo de simulación

SN65LVDT125A IBIS Model

SLLC199.ZIP (11 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (DBT) 38 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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