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Circuitos integrados LVDS, M-LVDS y PECL

SN65MLVD204A

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Transceptor M-LVDS semidúplex

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SN65MLVD204A

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Detalles del producto

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates (1) up to 100Mbps, Clock Frequencies up to 50MHz
  • Type-1 Receivers Incorporate 25mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)
  • Type-2 Receivers Provide an Offset (100mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1V to 3.4V of Common-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
  • 200Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)
  • Bus Pin ESD Protection Exceeds 8kV
  • Packages Available:
    • 8-Pin SOIC SN65MLVD200A, SN65MLVD204A
    • 14-Pin SOIC SN65MLVD202A, SN65MLVD205A
  • Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices

(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
  • Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates (1) up to 100Mbps, Clock Frequencies up to 50MHz
  • Type-1 Receivers Incorporate 25mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)
  • Type-2 Receivers Provide an Offset (100mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)
  • Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • –1V to 3.4V of Common-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
  • 200Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)
  • Bus Pin ESD Protection Exceeds 8kV
  • Packages Available:
    • 8-Pin SOIC SN65MLVD200A, SN65MLVD204A
    • 14-Pin SOIC SN65MLVD202A, SN65MLVD205A
  • Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices

(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)

The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.

The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.

The devices are characterized for operation from –40°C to 85°C.

The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.

The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.

The devices are characterized for operation from –40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet (Rev. E) PDF | HTML 01 mar 2024
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 22 jun 2023
Application brief How Far, How Fast Can You Operate MLVDS? 06 ago 2018
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 20 nov 2001

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

MLVD20XBEVM — Módulo de evaluación LVDS multipunto (M-LVDS) dúplex completo y semidúplex SN65MLVD203B y SN65MLVD20

Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

MLVD20XEVM — Módulo de evaluación M-LVDS

This evaluation module is for the SN65MLVD203B and SN65MLVD204B, which are M-LVDS transceivers.
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

SN65MLVD2-3EVM — SN65MLVD2-3EVM Módulo de evaluación

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)

Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

SN65MLVD204A IBIS Model

SLLC186.ZIP (16 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 8 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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Soporte y capacitación

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