SN75ALS164

Name: SN75ALS164
Brand: TI
SKU: SN75ALS164
Price: 4.177 USD

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Transceptor de bus de interfaz de uso general octal

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document-pdfAcrobat Octal General-Purpose Interface Bus Transceiver datasheet (Rev. C) (Inglés)

SN75ALS164

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Detalles del producto

Rating

Catalog

Operating temperature range (°C)

0 to 70

Rating

Catalog

Operating temperature range (°C)

0 to 70

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

8-Channel Bidirectional Transceiver
Designed to Implement Control Bus Interface
Designed for Multiple-Controller Systems
High-Speed Advanced Low-Power Schottky Circuitry
Low-Power Dissipation...46 mW Max Per Channel
Fast Propagation Times...20 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis...650 mV Typ
Bus-Terminating Resistors Provided on Driver Outputs
No Loading of Bus When Device Is Powered Down (V_CC = 0)
Power-Up/Power-Down Protection
(Glitch Free)

8-Channel Bidirectional Transceiver
Designed to Implement Control Bus Interface
Designed for Multiple-Controller Systems
High-Speed Advanced Low-Power Schottky Circuitry
Low-Power Dissipation...46 mW Max Per Channel
Fast Propagation Times...20 ns Max
High-Impedance pnp Inputs
Receiver Hysteresis...650 mV Typ
Bus-Terminating Resistors Provided on Driver Outputs
No Loading of Bus When Device Is Powered Down (V_CC = 0)
Power-Up/Power-Down Protection
(Glitch Free)

The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus.

The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during V_CC power-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output.

The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage V_CC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the terminal when disabled.

The SN75ALS164 is characterized for operation from 0°C to 70°C.

H = high level, L = low level, R = receive, T = transmit, X = irrelevant

Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.

Data transfer is noninverting in both directions.

ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI when the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.

The SN75ALS164 eight-channel general-purpose interface bus transceiver is a monolithic, high-speed, advanced low-power Schottky device designed to meet the requirements of IEEE Standard 488-1978. Each transceiver is designed to provide the bus-management and data-transfer signals between operating units of a multiple-controller instrumentation system. When combined with the SN75ALS160 octal bus transceiver, the SN75ALS164 provides the complete 16-wire interface for the IEEE 488 bus.

The SN75ALS164 features eight driver-receiver pairs connected in a front-to-back configuration to form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at the high-impedance state) during V_CC power-up and power-down transitions for glitch-free operation. The direction of data flow through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75ALS164 is identical to the SN75ALS162 with the addition of an OR gate to help simplify board layouts in several popular applications. The ATN and EOI signals are ORed to provide the ATN + EOI output, which is a standard totem-pole output.

The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high impedance to the bus when supply voltage V_CC is 0. The drivers are designed to handle loads up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for increased noise immunity. All receivers have 3-state outputs that present a high impedance to the terminal when disabled.

The SN75ALS164 is characterized for operation from 0°C to 70°C.

H = high level, L = low level, R = receive, T = transmit, X = irrelevant

Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.

Data transfer is noninverting in both directions.

ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI when the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.

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