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Circuitos integrados LVDS, M-LVDS y PECL

SN75LVDS051

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Controladores y receptores de línea diferencial de alta velocidad

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SN75LVDS051

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Detalles del producto

Function Transceiver Protocols LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 155 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
Function Transceiver Protocols LVDS Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 155 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Signaling Rates up to 155 Mbps
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100 Load
  • LVTTL Input Levels are 5 V Tolerant
  • Driver is High Impedance When Disabled or With VCC < 1.5 V
  • Receiver has Open-Circuit Fail Safe
  • Surface-Mount Packaging
    • D Package (SOIC)
  • Characterized For Operation From
    0°C to 70°C
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
  • Signaling Rates up to 155 Mbps
  • Operates From a Single 3.3-V Supply
  • Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100 Load
  • LVTTL Input Levels are 5 V Tolerant
  • Driver is High Impedance When Disabled or With VCC < 1.5 V
  • Receiver has Open-Circuit Fail Safe
  • Surface-Mount Packaging
    • D Package (SOIC)
  • Characterized For Operation From
    0°C to 70°C

The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 155 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100 load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are characterized for operation from 0°C to 70°C.

The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 155 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100 load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

The SN75LVDS179, SN75LVDS180, SN75LVDS050, and SN75LVDS051 are characterized for operation from 0°C to 70°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet High-Speed Differential Line Drivers And Receivers datasheet (Rev. A) 09 mar 2000
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDS051 IBIS Model

SLLM004.ZIP (51 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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SOIC (D) 16 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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