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Circuitos integrados LVDS, M-LVDS y PECL

SN75LVDS391

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Controlador LVDS cuádruple

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SN75LVDS391

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Detalles del producto

Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 630 Input signal LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) 0 to 70
Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 630 Input signal LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Four (’391), Eight (’389), or Sixteen (’387) Line
    Drivers Meet or Exceed the Requirements of ANSI
    EIA/TIA-644 Standard
  • Designed for Signaling Rates Up to 630 Mbps
    With Very Low Radiation (EMI)
  • Low-Voltage Differential Signaling With Typical
    Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Times Less Than 2.9 ns
  • Output Skew Is Less Than 150 ps
  • Part-to-Part Skew Is Less Than 1.5 ns
  • 35-mW Total Power Dissipation in Each Driver
    Operating at 200 MHz
  • Driver Is High-Impedance When Disabled or With
    VCC < 1.5 V
  • SN65’ Version Bus-Pin ESD Protection Exceeds
    15 kV
  • Packaged in Thin Shrink Small-Outline Package
    With 20-mil Pin Pitch
  • Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
    Tolerant
  • Four (’391), Eight (’389), or Sixteen (’387) Line
    Drivers Meet or Exceed the Requirements of ANSI
    EIA/TIA-644 Standard
  • Designed for Signaling Rates Up to 630 Mbps
    With Very Low Radiation (EMI)
  • Low-Voltage Differential Signaling With Typical
    Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Times Less Than 2.9 ns
  • Output Skew Is Less Than 150 ps
  • Part-to-Part Skew Is Less Than 1.5 ns
  • 35-mW Total Power Dissipation in Each Driver
    Operating at 200 MHz
  • Driver Is High-Impedance When Disabled or With
    VCC < 1.5 V
  • SN65’ Version Bus-Pin ESD Protection Exceeds
    15 kV
  • Packaged in Thin Shrink Small-Outline Package
    With 20-mil Pin Pitch
  • Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
    Tolerant

This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.

The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.

This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.

The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SNx5LVDS3xx High-Speed Differential Line Drivers datasheet (Rev. G) PDF | HTML 14 ene 2016
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDS391 IBIS Model (Rev. A)

SLLC090A.ZIP (4 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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