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SN75LVDT390

ACTIVO

Receptor LVDS cuádruple con configuración de pines de flujo de 250 Mbps

Detalles del producto

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Four- (’390), Eight- (’388A), or Sixteen- (’386)
    Line Receivers Meet or Exceed the Requirements
    of ANSI TIA/EIA-644 Standard
  • Integrated 110-Ω Line Termination
    Resistors on LVDT Products
  • Designed for Signaling Rates Up to 250 Mbps
  • SN65 Versions Bus-Terminal ESD Exceeds
    15 kV
  • Operates From a Single 3.3-V Supply
  • Typical Propagation Delay Time of 2.6 ns
  • Output Skew 100 ps (Typical) Part-To-Part
    Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pinout
  • Packaged in Thin Shrink Small-Outline
    Package With 20-mil Terminal Pitch
  • Four- (’390), Eight- (’388A), or Sixteen- (’386)
    Line Receivers Meet or Exceed the Requirements
    of ANSI TIA/EIA-644 Standard
  • Integrated 110-Ω Line Termination
    Resistors on LVDT Products
  • Designed for Signaling Rates Up to 250 Mbps
  • SN65 Versions Bus-Terminal ESD Exceeds
    15 kV
  • Operates From a Single 3.3-V Supply
  • Typical Propagation Delay Time of 2.6 ns
  • Output Skew 100 ps (Typical) Part-To-Part
    Skew Is Less Than 1 ns
  • LVTTL Levels Are 5-V Tolerant
  • Open-Circuit Fail Safe
  • Flow-Through Pinout
  • Packaged in Thin Shrink Small-Outline
    Package With 20-mil Terminal Pitch

This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387, respectively), over 200 million data transfers per second in single-edge clocked systems are possible with little power.

The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail.

Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, the 8- or 16-channel driver (the SN65LVDS389 or SN65LVDS387, respectively), over 200 million data transfers per second in single-edge clocked systems are possible with little power.

The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

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Documentación técnica

star =Principal documentación para este producto seleccionada por TI
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Ver todo 5
Tipo Título Fecha
* Data sheet High-Speed Differential Line Receivers. datasheet (Rev. I) 29 jul 2014
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 may 2018
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SN65LVDT390, SN75LVDT390 IBIS Model

SLLC047.ZIP (4 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

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