The TLC69699-Q1 SPI-compatible connectivity enables TLC696xx-Q1 device family to be controlled using a standard SPI controller. The device features an internal oscillator to generate the continuous clock required by the TLC696xx-Q1 device family. Jitter can be added to the continuous clock for EMI enhancement. The transmitted data is aligned to the continuous clock to maintain the timing requirements of the CCSI interface.
TLC69699-Q1 incorporates reporting of faults in both the TLC696xx-Q1 daisy chain and TLC69699-Q1 internal. Data transmission of register and brightness to the TLC696xx-Q1 daisy chain is CRC protected by TLC69699-Q1. In addition, both the data and continuous clock lines are guarded by TLC69699-Q1 for stuck-at faults.
The TLC69699-Q1 SPI-compatible connectivity enables TLC696xx-Q1 device family to be controlled using a standard SPI controller. The device features an internal oscillator to generate the continuous clock required by the TLC696xx-Q1 device family. Jitter can be added to the continuous clock for EMI enhancement. The transmitted data is aligned to the continuous clock to maintain the timing requirements of the CCSI interface.
TLC69699-Q1 incorporates reporting of faults in both the TLC696xx-Q1 daisy chain and TLC69699-Q1 internal. Data transmission of register and brightness to the TLC696xx-Q1 daisy chain is CRC protected by TLC69699-Q1. In addition, both the data and continuous clock lines are guarded by TLC69699-Q1 for stuck-at faults.