The TPS7A4501-SP is a low-dropout (LDO) regulator optimized for fast-transient response. The 5962-1222402VHA can supply 750 mA of output current with a dropout voltage of 300 mV. The 5962R1222403VXC can supply 1.5 A of output current with a dropout voltage of 320 mV. Quiescent current is well controlled; it does not rise in dropout, as with many other regulators. In addition to fast transient response, the TPS7A4501-SP regulator has very-low output noise, which makes it ideal for sensitive RF supply applications.
Output voltage range is from 1.21 to 20 V. The TPS7A4501-SP is stable with output capacitance as low as 10 µF. Small ceramic capacitors can be used without the necessary addition of ESR, as is common with other regulators. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting, and reverse-current protection. The device is available as an adjustable device with a 1.21-V reference voltage. The 5962-1222402VHA is available in 10-pin CFP (U) package and 5962R1222403VXC is available in thermally-enhanced 10-pin CFP (HKU) package. Known good die (KGD) option is available for both 5962-1222402V9A for non-RHA version and 5962R1222403V9A for RHA.
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ADC12DJ3200EVMCVAL 是一款評估 ADC12DJ3200QML-SP 裝置的評估模組 (EVM)。ADC12DJ3200QML-SP 為航太級、低功耗、12位元、雙 3.2-GSPS/單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)，具有緩衝類比輸入、整合式數位降壓轉換器和 JESD204B 介面。整合式數位降壓轉換器，搭載可編程 NCO 和降取設定，包括無降取 12 位元與 8 位元 ADC 輸出。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。板載 LMX2582 時鐘合成器和 LMK04832 JESD204B 時鐘產生器，可配置為提供完整 (...)
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The TPS7A4501 is a low-dropout (LDO) regulator optimized for fast transient respone.
It provides thermally enhanced small size solution capable of delivering 1.5A load current, and has low output noise for sensitive RF applicatons.
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類比輸入路徑可選擇將 6.5-GHz LMH5401-SP 做為單端至差動增益區塊，或繞過放大器並以差動訊號驅動 ADC。放大器後則為 12 位元、雙 1.6-GSPS 或單 3.2-GSPS ADC12D1620QML-SP。這些高效能元件皆有必要的電源、微控制器和溫度感測器裝置支援。
TSW12D1620EVM-CVAL (...)
The parallel low-dropout (LDO) calculator is a Microsoft® Excel®-based tool that provides worst-case analysis for parallel LDO regulators using ballast resistors. The tool helps the user identify the minimum number of parallel LDO regulators required and optimum ballast resistance for a (...)
As FPGA and ASIC technology advances, the core voltage requirements get lower but the current demand is larger. The newest space grade FPGAs and ASICS require low voltage and high currents for their core power consumption. These high (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CFP (HKU) | 10 | Ultra Librarian |
| CFP (U) | 10 | Ultra Librarian |
| DIESALE (KGD) | — |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
Parallel LDO Calculator using ballast resistors
Initial Release