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線性與低壓差 (LDO) 穩壓器

TPS7A33

現行

具啟用功能的 1A、高 PSRR、負可調式超低壓差電壓穩壓器

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產品規格表

TPS7A33

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output, Negative Output Iout (max) (A) 1 Vin (max) (V) -3 Vin (min) (V) -36 Vout (max) (V) -1.2 Vout (min) (V) -33 Fixed output options (V) -1.2 Noise (µVrms) 16 Iq (typ) (mA) 0.21 Thermal resistance θJA (°C/W) 31 Rating Catalog Load capacitance (min) (µF) 10 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2.5 PSRR at 100 KHz (dB) 64 Dropout voltage (Vdo) (typ) (mV) 290 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Negative Output Iout (max) (A) 1 Vin (max) (V) -3 Vin (min) (V) -36 Vout (max) (V) -1.2 Vout (min) (V) -33 Fixed output options (V) -1.2 Noise (µVrms) 16 Iq (typ) (mA) 0.21 Thermal resistance θJA (°C/W) 31 Rating Catalog Load capacitance (min) (µF) 10 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2.5 PSRR at 100 KHz (dB) 64 Dropout voltage (Vdo) (typ) (mV) 290 Operating temperature range (°C) -40 to 125
VQFN (RGW) 20 25 mm² 5 x 5
  • Input Voltage Range: –3 V to –36 V
  • Noise:
    • 16 µVRMS (10 Hz to 100 kHz)
  • Power-Supply Ripple Rejection:
    • 72 dB (10 kHz)
  • Adjustable Output: –1.18 V to –33 V
  • Maximum Output Current: 1 A
  • Stable With Ceramic Capacitors ≥ 10 µF
  • Built-In Current-Limit and Thermal Shutdown
    Protection
  • Available in an External Heatsink-Capable, High
    Thermal Performance TO-220 Package
  • Operating Temperature Range:
    –40°C to 125°C
  • Input Voltage Range: –3 V to –36 V
  • Noise:
    • 16 µVRMS (10 Hz to 100 kHz)
  • Power-Supply Ripple Rejection:
    • 72 dB (10 kHz)
  • Adjustable Output: –1.18 V to –33 V
  • Maximum Output Current: 1 A
  • Stable With Ceramic Capacitors ≥ 10 µF
  • Built-In Current-Limit and Thermal Shutdown
    Protection
  • Available in an External Heatsink-Capable, High
    Thermal Performance TO-220 Package
  • Operating Temperature Range:
    –40°C to 125°C

The TPS7A33 series of linear regulators are negative voltage (–36 V), ultralow-noise (16-µVRMS, 72-dB PSRR) linear regulators capable of sourcing a maximum load of 1 A.

The TPS7A33 series include a complementary metal oxide semiconductor (CMOS) logic-level-compatible enable pin (EN) to allow for user-customizable power management schemes. Other features available include built-in current limit and thermal shutdown features to protect the device and system during fault conditions.

The TPS7A33 family is designed using bipolar technology primarily for high-accuracy, high-precision instrumentation applications, where clean voltage rails are critical to maximize system performance. This feature makes it ideal to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

In addition, the TPS7A33 family of linear regulators is suitable for post DC-DC converter regulation. By filtering out the output voltage ripple inherent to DC-DC switching conversion, maximum system performance is ensured in sensitive instrumentation, medical, test and measurement, audio, and RF applications.

For applications where positive and negative high-performance rails are required, consider the TPS7A4700 positive high-voltage, ultralow-noise, low-dropout linear regulator as well.

The TPS7A33 series of linear regulators are negative voltage (–36 V), ultralow-noise (16-µVRMS, 72-dB PSRR) linear regulators capable of sourcing a maximum load of 1 A.

The TPS7A33 series include a complementary metal oxide semiconductor (CMOS) logic-level-compatible enable pin (EN) to allow for user-customizable power management schemes. Other features available include built-in current limit and thermal shutdown features to protect the device and system during fault conditions.

The TPS7A33 family is designed using bipolar technology primarily for high-accuracy, high-precision instrumentation applications, where clean voltage rails are critical to maximize system performance. This feature makes it ideal to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

In addition, the TPS7A33 family of linear regulators is suitable for post DC-DC converter regulation. By filtering out the output voltage ripple inherent to DC-DC switching conversion, maximum system performance is ensured in sensitive instrumentation, medical, test and measurement, audio, and RF applications.

For applications where positive and negative high-performance rails are required, consider the TPS7A4700 positive high-voltage, ultralow-noise, low-dropout linear regulator as well.
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類型 標題 日期
* Data sheet TPS7A33 –36-V, 1-A, Ultralow-Noise Negative Voltage Regulator datasheet (Rev. D) PDF | HTML 2013年 10月 18日
White paper Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022年 12月 14日
White paper Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022年 12月 13日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Technical article Design a pre-tracking regulator, part 2: for a negative LDO PDF | HTML 2019年 4月 26日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

DDC2256AEVM — DDC2256A 256 通道電流輸入類比轉數位轉換器評估模組

The DDC2256AEVM evaluation module  (EVM)  is  an  evaluation  kit  for the DDC2256A,  a  256-channel,  current  input,  24-bit analog-to-digital (A/D) converter. The EVM kit, comprised of a DUT board and a capture board, contains two DDC2256A (...)

使用指南: PDF
要求
模擬型號

TPS7A3301 PSpice Transient Model

SBVM105.ZIP (32 KB) - PSpice Model
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模擬型號

TPS7A3301 TINA-TI Transient Reference Design

SBVM399.ZIP (12 KB) - TINA-TI Reference Design
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模擬型號

TPS7A3301 TINA-TI Transient Spice Model

SBVM400.ZIP (5 KB) - TINA-TI Spice Model
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模擬型號

TPS7A3301 Unencrypted PSpice Transient Model

SBVM665.ZIP (0 KB) - PSpice Model
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計算工具

PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator

The parallel low-dropout (LDO) calculator is a Microsoft® Excel®-based tool that provides worst-case analysis for parallel LDO regulators using ballast resistors. The tool helps the user identify the minimum number of parallel LDO regulators required and optimum ballast resistance for a (...)

支援產品和硬體

支援產品和硬體

產品
線性與低壓差 (LDO) 穩壓器
TPS7A33 — 具啟用功能的 1A、高 PSRR、負可調式超低壓差電壓穩壓器 TPS7A47 — 具有啟用功能的 1A、36V、低雜訊、高 PSRR、低壓差電壓穩壓器 TPS7A47-Q1 — 具有啟用功能的汽車 1-A、36-V、低雜訊、高 PSRR、低壓差電壓穩壓器 TPS7A4701-EP — 強化型 36-V、1-A、4-μVRMS、RF LDO 電壓穩壓器 TPS7A52 — 2-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差 (LDO) 電壓穩壓器 TPS7A52-Q1 — 車用 2-A、低 VIN (1.1-V)、低雜訊、高準確度、低壓降 (LDO) 電壓穩壓器 TPS7A53 — 3-A、低輸入電壓 (1.1 V) 低雜訊高準確度超低壓差 (LDO) 電壓穩壓器 TPS7A53-Q1 — 車用 3A、低 VIN (1.1V)、低雜訊、高準確度、低壓降 (LDO) 電壓穩壓器 TPS7A53A-Q1 — 車用 3-A、低 VIN 5.6-µVRMS 低雜訊高準確度低壓降電壓穩壓器 TPS7A53B — 具有 0.5-V 低 VREF 的 3-A ， 1.1-V ，低 VIN ，低雜訊高準確度超低壓差電壓穩壓器 TPS7A54 — 4-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差 (LDO) 電壓穩壓器 TPS7A54-Q1 — 車用 4-A、低 VIN (1.1-V)、低雜訊、高準確度、低壓差 (LDO) 電壓穩壓器 TPS7A57 — 5-A、低輸入電壓、低雜訊、高準確度、低壓差 (LDO) 電壓穩壓器 TPS7A83A — 具有電源良好功能的 2-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差電壓穩壓器 TPS7A84A — 具有電源良好功能的 3-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差電壓穩壓器 TPS7A85A — 具有電源良好功能的 4-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差電壓穩壓器 TPS7A94 — 1-A、超低雜訊、超高 PSRR、射頻電壓穩壓器 TPS7B7702-Q1 — 汽車 300-mA、無電池 (40-V)、雙通道可調整天線低壓差電壓穩壓器 TPS7A8300 — 2-A、低 VIN、低 2-A、低 VIN、低雜訊、超低壓降電壓穩壓器具有高準確度、低雜訊的良好電源，超低壓降電壓穩壓器具有高準確度的良好電源 TPS7A84 — 具有高準確度且具有電源良好功能的 3-A、低 VIN、低雜訊、超低壓差電壓穩壓器 TPS7A85 — 具有高準確度且具有電源良好功能的 4-A、低 VIN、低雜訊、超低壓差電壓穩壓器 TPS7A96 — 2-A、超低雜訊、超高 PSRR 射頻電壓穩壓器 TPS7A4501-SP — 抗輻射、QMLV、1.5-V 至 20-V 輸入 1.5-A 低壓降 (LDO) 穩壓器 TPS7H1111-SP — 抗輻射、QMLV 和 QMLP、1.5-A、超低雜訊高 PSRR 低壓降 (LDO) 穩壓器 TPS7H1111-SEP — 耐輻射、1.5-A、超低雜訊、超高 PSRR RF LDO 穩壓器
硬體開發
開發板
TPS7A57EVM-081 — 適用於 5-A 低雜訊高準確度低壓差 (LDO) 電壓穩壓器的 TPS7A57 評估模組
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參考設計

TIDA-01371 — 適用於超音波系統的可編程 ±100V、高電流、浮點線性穩壓器參考設計

Ultrasound transmitters require a stable programmable DC power source to drive high current into piezo transducers during the transmission. The TIDA-01371 reference design demonstrates a positive and negative linear regulator that can provide output voltages varying from ±2.5 to (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01458 — 用於超音波 CW 脈衝產生器的低雜訊固定降壓 ±2.5 至 ±12V 輸出電壓 3A 電源參考設計

This reference design allows a digitally programmable power supply to power an ultrasound transmit circuit for continuous wave (CW) mode from a 24-V bus. There are two outputs adjustable from ±2.5 to ±12 V under user software control. These outputs can provide up to 2 A with very low (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01027 — 在 12.8 GSPS 資料採集系統中發揮最大效能的低雜訊電源供應參考設計

This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能

此參考設計可解決與新興 5G 適配應用相關，例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化，這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器，透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能，在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果，以進一步降低偏斜。此設計也具備搭載 (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00684 — 高頻寬任意波形產生器參考設計：DC 或 AC 耦合，高壓輸出

In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
Design guide: PDF
電路圖: PDF
參考設計

PMP10651 — 適用於含所有防護的 12V 電池之 2.2 MHz 切換同步雙電源參考設計

PMP10651 is a low noise, multi-output SMPS design where LM53603 is used in Inverting Buck-Boost Fly buck topology to generate positive and negative supply needed in multiple noise sensitive applications such as powering High Speed Video Amplifier, RF amplifier, Precision Low noise amplifier (...)
Test report: PDF
電路圖: PDF
參考設計

PMP8372 — 具有低雜訊 LDO 分裂軌 (±5V) 輸出電壓的 40V 雙路 1A 電源模組參考設計

The PMP8372 design is optimized for small size and uses the TPS84250 step-down power module on the top- side with the TPS84259 negative output power module on the bottom-side to implement both positive and negative output voltages from a 12V/24V source. The output voltages can be adjusted from (...)
Test report: PDF
電路圖: PDF
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