TPS7H2140-SEP
- Vendor item drawing available, VID V62/23610
- Total ionizing dose (TID) characterized to 30 krad(Si)
- RLAT (radiation lot acceptance testing) to 20 krad(Si)
- Single-event effects (SEE) characterized
- Single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune to linear energy transfer (LET) of 43 MeV-cm 2/mg
- Single-event transient (SET) and single-event functional interrupt (SEFI) characterized to effective linear energy transfer (LET) of 43 MeV-cm 2/mg
- Quad-channel 160-mΩ eFuse with full diagnostics and current-sense analog output
- Wide operating voltage 4.5 V to 32 V
- Ultra-low standby current < 500 nA
- High-accuracy current sense: ±15% when I LOAD ≥ 25 mA
- Adjustable current limit with external resistor (R CL), with accuracy of ±15% when I LOAD ≥ 500 mA
- Protection
- Short-to-GND protection by current limit (internal or external)
- Thermal shutdown with latch off option and thermal swing
- Inductive load negative voltage clamp with optimized slew rate
- Loss-of-GND and loss-of-power protection
- Diagnostics
- Overcurrent and short-to-ground detection
- Open-load and short-to-power detection
- Global fault report for fast interrupt
- 28-pin thermally-enhanced PWP package
- Space Enhanced Plastic (SEP)
- Available in military (–55°C to 125°C) temp range
The TPS7H2140-SEP device is a fully protected quad-channel eFuse with four integrated 160-mΩ NMOS power FETs.
Full diagnostics and high-accuracy current sense enables intelligent control of the loads.
An external adjustable current limit improves the reliability of whole system by limiting the inrush or overload current.
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開發板
TPS7H2140EVM — 適用於耐輻射塑膠四通道 eFuse 的 TPS7H2140-SEP 評估模組
TPS7H2140-SEP 評估模組展示了四通道 eFuse 的運作。該電路板配置為測試平行輸出通道,可以進行自訂以分割輸出通道和/或自訂裝置的其他功能。
計算工具
This tool suggests suitable TVS for given system parameters and abs max voltage rating of the device.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HTSSOP (PWP) | 28 | Ultra Librarian |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。