AM2631

Processor Cores:

• Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
  • 16KB I-cache with 64-bit ECC per CPU core
  • 16KB D-cache with 32-bit ECC per CPU core
  • 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
  • Lockstep or Dual-core capable clusters

Memory Subsystem:

• 2MB of On-Chip RAM (OCSRAM)
  • 4 Banks x 512KB
  • ECC error protection
  • Internal DMA engine support

System on Chip (SoC) Services and Architecture:

• 1x EDMA to support data movement functions
• Device Boot supported from the following interfaces:
  • UART (Primary/Backup)
  • QSPI NOR Flash (4S/1S) (Primary)
• Interprocessor communication modules
  • SPINLOCK module for synchronizing processes running on multiple cores
  • MAILBOX functionality implemented through CTRLMMR registers
• Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers

Media and Data Storage:

• 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
• General-Purpose Memory Controller (GPMC)
  • 16-bit parallel data bus with 22-bit address bus
  • Up to 4MB addressable memory space
  • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

• 6x Universal Asynchronous RX-TX (UART)
• 5x Serial Peripheral Interface (SPI) controllers
• 5x Local Interconnect Network (LIN) ports
• 4x Inter-Integrated Circuit (I2C) ports
• 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
• 1x Quad Serial Peripheral Interface (QSPI)
• 4x Fast Serial Interface Transmitters (FSITX)
• 4x Fast Serial Interface Receivers (FSIRX)
• Up to 139 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

• Real-time Control Subsystem (CONTROLSS)
• Flexible Input/Output Crossbars (XBAR)
• 5x 12-bit Analog-to-Digital Converters (ADC)
  • 6-input SAR ADC up to 4 MSPS
    • 6x Single-ended channels OR
    • 3x Differential channels
  • Highly Configurable ADC Digital Logic
    • XBAR Start of Conversion Triggers (SOC)
    • User-defined Sample and Hold (S+H)
    • Flexible Post-Processing Blocks (PPB)
• 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
• 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
• 1x 12-bit Digital-to-Analog Converter (DAC)
• 32x Pulse Width Modulation (EPWM) modules
  • Single or Dual PWM channels
  • Advanced PWM Configurations
  • Extended HRPWM time resolution
• 10x Enhanced Capture (ECAP) modules
• 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
• 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
• Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

• Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
  • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
    • Deterministic Hardware
    • Dynamic Firmware
  • 20-channel enhanced input (eGPI) per PRU
  • 20-channel enhanced output (eGPO) per PRU
  • Embedded Peripherals and Memory
    • 1x UART, 1x ECAP
    • 1x MDIO, 1x IEP,
    • 1x 32KB Shared General Purpose RAM
    • 2x 8KB Shared Data RAM
    • 1x 16KB IRAM per PRU
    • ScratchPad (SPAD), MAC/CRC
  • Digital encoder and sigma-delta control loops
  • The PRU-ICSS enables advanced industrial protocols including:
    • EtherCAT, Ethernet/IP™,
    • PROFINET, IO-Link for order
  • Dedicated Interrupt Controller (INTC)
  • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

• Integrated Ethernet switch supporting two external ports
  • RMII (10/100) or RGMII (10/100/1000)
  • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
  • Clause 45 MDIO PHY management
  • 512x ALE engine-based Packet Classifiers
  • Priority flow control with up to 2KB packet size
  • Four CPU hardware interrupt pacing
  • IP/UDP/TCP checksum offload in hardware

Security:

• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Secure boot support
  • Device Take Over Protection
  • Hardware-enforced root-of-trust
  • Authenticated boot
  • SW Anti-rollback protection
• Debug security
  • Secure device debug only after proper authentication
  • Ability to disable device debug functionality
• Device ID and Key Management
  • Support for OTP Memory (FUSEROM)
    • Store root keys & other security fields
  • Separate EFUSE controllers and FUSE ROMs
  • Unique Public Device Identifiers (UIDs)
• Memory Protection Units (MPU)
  • Dedicated Arm® MPU per Cortex®-R5F core
  • System MPU - present at various interfaces in the SoC (MPU or Firewall)
  • 8-16 Programmable Regions
    • Enable/Privilege ID
    • Start/End Address
    • Read/Write/Cachable
    • Secure/Non-Secure
• Cryptographic Acceleration
  • Cryptographic cores with DMA Support
  • AES - 128/192/256-bit key sizes
  • SHA2 - 256/384/512-bit support
  • DRBG with pseudo and true random number generator
  • PKA (public key accelerator) to assist in RSA/ECC processing

Functional Safety:

• Enables design of systems with functional safety requirements
  • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
  • ECC or parity on calculation-critical memories
  • Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
  • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
• Functional Safety-Compliant [Industrial]
  • Developed for functional safety applications
  • Documentation to be made available to aid IEC 61508 functional safety system design
  • Systematic capability up to SIL-3
  • Hardware integrity up to SIL-3
  • Safety-related certification
    • IEC 61508 certified up to SIL-3 by TUV SUD
• Functional Safety-Compliant [Automotive]
  • Developed for functional safety applications
  • Documentation to be made available to aid ISO 26262 functional safety system design
  • Systematic capability up to ASIL-D
  • Hardware integrity up to ASIL-D
  • Safety-related certification
    • ISO 26262 certified up to ASIL-D by TUV SUD

Technology / Package:

• AEC-Q100 qualified for automotive applications
• 45-nm technology
• ZCZ Package
  • 324-pin NFBGA
  • 15.0 mm x 15.0 mm
  • 0.8 mm pitch