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Serializadores-deserializadores de alta velocidad
Serializadores-deserializadores FPD-Link

DS90CF564

ACTIVO

LVDS para enlace de pantalla plana (FPD) a color de 18 bits y 65 MHz

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DS90CF564

ACTIVO
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Detalles del producto

Function Deserializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
Function Deserializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 20 to 65 MHz Shift Clk Support
  • Up to 171 Mbytes/s Bandwidth
  • Cable Size is Reduced to Save Cost
  • 290 mV Swing LVDS Devices for Low EMI
  • Low Power CMOS Design (< 550 mW typ)
  • Power-down Mode Saves Power (< 0.25 mW)
  • PLL Requires No External Components
  • Low Profile 48-Lead TSSOP Package
  • Falling Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Single Pixel Per Clock XGA (1024 x 768)
  • Supports VGA, SVGA, XGA and Higher
  • 1.3 Gbps Throughput

All trademarks are the property of their respective owners.

  • 20 to 65 MHz Shift Clk Support
  • Up to 171 Mbytes/s Bandwidth
  • Cable Size is Reduced to Save Cost
  • 290 mV Swing LVDS Devices for Low EMI
  • Low Power CMOS Design (< 550 mW typ)
  • Power-down Mode Saves Power (< 0.25 mW)
  • PLL Requires No External Components
  • Low Profile 48-Lead TSSOP Package
  • Falling Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Single Pixel Per Clock XGA (1024 x 768)
  • Supports VGA, SVGA, XGA and Higher
  • 1.3 Gbps Throughput

All trademarks are the property of their respective owners.

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display(FPD) Link - 65 MHz datasheet (Rev. E) 17 abr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 ago 2017
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 may 2004
Application note AN-1056 STN Application Using FPD-Link 14 may 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 may 2004

Diseño y desarrollo

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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  • Monitoreo continuo de confiabilidad
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