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DS90CR288A

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Receptor Channel Link LVDS de +3.3 V, 28 bits, 85 MHz y flanco de subida con luz estroboscópica de d

Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • 2.5 / 0 ns Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.38 Gbps Throughput
  • Up to 297.5 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • 2.5 / 0 ns Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.38 Gbps Throughput
  • Up to 297.5 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) 05 mar 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 nov 2018
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 ene 2016
EVM User's guide 28-Bit Channel Link SerDes Evaluation Board 20-85MHz User Guide 25 ene 2012
Design guide Channel Link I Design Guide 29 mar 2007
Application note Multi-Drop Channel-Link Operation 04 oct 2004
Application note CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 05 oct 1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

FLINK3V8BT-85 — Kit de evaluación para la familia FPD-Link de dispositivos LVDS serializadores y deserializadores

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

Guía del usuario: PDF
Modelo de simulación

DS90CR288A IBIS Model

SNLM040.ZIP (5 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (DGG) 56 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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