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DS92LV0412

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Deserializador Channel Link II de 5 MHz a 50 MHz con interfaz paralela LVDS

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DS92LV0412

ACTIVO
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Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² 7 x 7
  • 5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data
    3-bit Control at 5 – 50 MHz
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Serial CML Terminations
  • AT–SPEED BIST Mode and Status Pin
  • Optional I2C Compatible Serial Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • 1.8V or 3.3V Compatible Control Pin Interface
  • >8 kV ESD (HBM) Protection
  • -40° to +85°C Temperature Range

    • SERIALIZER – DS92LV0411

  • Data Scrambler for Reduced EMI
  • DC–Balance Encoder for AC Coupling
  • Selectable Output VOD and Adjustable De-Emphasis

    • DESERIALIZER – DS92LV0412

  • Random Data Lock; No Reference Clock Required
  • Adjustable Input Receiver Equalization
  • EMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select)

All trademarks are the property of their respective owners.

  • 5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data
    3-bit Control at 5 – 50 MHz
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Serial CML Terminations
  • AT–SPEED BIST Mode and Status Pin
  • Optional I2C Compatible Serial Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • 1.8V or 3.3V Compatible Control Pin Interface
  • >8 kV ESD (HBM) Protection
  • -40° to +85°C Temperature Range

    • SERIALIZER – DS92LV0411

  • Data Scrambler for Reduced EMI
  • DC–Balance Encoder for AC Coupling
  • Selectable Output VOD and Adjustable De-Emphasis

    • DESERIALIZER – DS92LV0412

  • Random Data Lock; No Reference Clock Required
  • Adjustable Input Receiver Equalization
  • EMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select)

All trademarks are the property of their respective owners.

The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair.

The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation.

The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS.

The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair.

The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation.

The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS.
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Documentación técnica

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Tipo Título Fecha
* Data sheet DS92LV0411/12 5 - 50MHz Ch Link II SER/DES with LVDS Parallel Interface datasheet (Rev. B) 16 abr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 nov 2018
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 29 abr 2013
User guide LV04EVK01 Channel Link to Channel Link II Converter Evaluation Kit 01 feb 2012
Design guide Channel Link II Design Guide 21 ene 2011

Diseño y desarrollo

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Modelo de simulación

DS92LV0412 IBIS Model

SNLM129.ZIP (172 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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WQFN (RHS) 48 Ultra Librarian
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Pedidos y calidad

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  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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