Inicio Interfaz Otras interfaces

DS92LV2412

ACTIVO

Deserializador Channel Link II de 24 bits y 5 MHz a 50 MHz

Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (NKB) 60 81 mm² 9 x 9
  • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
  • Application Payloads up to 1.2 Gbps
  • AC Coupled Interconnects: STP up to 10 m or
    Coax 20+m
  • 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • Integrated Terminations on Ser and Des
  • AT-SPEED BIST Mode and Reporting Pin
  • Configurable by Pins or I2C Compatible Serial
    Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • >8 kV HBM ESD Rating
  • SERIALIZER — DS92LV2411
    • Supports Spread Spectrum Clocking (SSC) on
      Inputs
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
      De-emphasis
  • DESERIALIZER — DS92LV2412
    • Random Data Lock; no Reference Clock
      Required
    • Adjustable Input Receiver Equalization
    • LOCK (Real Time Link Status) Reporting Pin
    • Selectable Spread Spectrum Clock Generation
      (SSCG) and Output Slew Rate Control (OS) to
      Reduce EMI
  • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
  • Application Payloads up to 1.2 Gbps
  • AC Coupled Interconnects: STP up to 10 m or
    Coax 20+m
  • 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • Integrated Terminations on Ser and Des
  • AT-SPEED BIST Mode and Reporting Pin
  • Configurable by Pins or I2C Compatible Serial
    Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • >8 kV HBM ESD Rating
  • SERIALIZER — DS92LV2411
    • Supports Spread Spectrum Clocking (SSC) on
      Inputs
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
      De-emphasis
  • DESERIALIZER — DS92LV2412
    • Random Data Lock; no Reference Clock
      Required
    • Adjustable Input Receiver Equalization
    • LOCK (Real Time Link Status) Reporting Pin
    • Selectable Spread Spectrum Clock Generation
      (SSCG) and Output Slew Rate Control (OS) to
      Reduce EMI

The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables.

In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to +85°C.

The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables.

In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to +85°C.

Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 4
Tipo Título Fecha
* Data sheet DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer datasheet (Rev. E) PDF | HTML 09 feb 2015
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 29 abr 2013
User guide LV24EVK01 Channel Link II Ser/Des Evaluation Kit User Guide 25 ene 2012
Design guide Channel Link II Design Guide 21 ene 2011

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

DS92LV2412 IBIS Model

SNLM125.ZIP (146 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
WQFN (NKB) 60 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos