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Circuitos integrados LVDS, M-LVDS y PECL

EQ50F100

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Ecualizador de plano posterior de 1 Gbps a 6.25 Gbps

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EQ50F100

COMPRA POR ÚLTIMA VEZ
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Detalles del producto

Function Equalizer Protocols CML Number of transmitters 1 Number of receivers 1 Supply voltage (V) 1.8 Signaling rate (Mbps) 6250 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
Function Equalizer Protocols CML Number of transmitters 1 Number of receivers 1 Supply voltage (V) 1.8 Signaling rate (Mbps) 6250 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
WSON (NGG) 6 9 mm² 3 x 3
  • Recovers 6.25 Gbps signals after 30" of FR4
  • Single 1.8V power supply
  • Low power consumption: 85mW
  • Equalize up to 20dB loss at 2.5 GHz
  • 35 ps residual deterministic jitter at 5 Gbps
  • On-chip CML terminations
  • Small 3 mm x 3 mm 6-pin leadless LLP package
  • Recovers 6.25 Gbps signals after 30" of FR4
  • Single 1.8V power supply
  • Low power consumption: 85mW
  • Equalize up to 20dB loss at 2.5 GHz
  • 35 ps residual deterministic jitter at 5 Gbps
  • On-chip CML terminations
  • Small 3 mm x 3 mm 6-pin leadless LLP package

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.
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Documentación técnica

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Tipo Título Fecha
* Data sheet EQ50F100 1Gbps - 6.25 Gbps Backplane Equalizer datasheet (Rev. D) 14 abr 2005

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje