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Drivers de compuerta aislados

ISO5852S

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Controlador de puerta aislada monocanal de 5.7 kVrms, 2.5 A/5 A con salida dividida, STO y funciones

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ISO5852S

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Detalles del producto

Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.
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Documentación técnica

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* Data sheet ISO5852S High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet (Rev. C) PDF | HTML 30 may 2023
Certificate VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. S) 29 feb 2024
Application note Digital Isolator Design Guide (Rev. G) PDF | HTML 13 sep 2023
User guide UCC217xx and ISO5x5x Half-Bridge EVM User's Guide for Wolfspeed 1200-V SiC 01 sep 2023
White paper Circuit Board Insulation Design According to IEC60664 for Motor Drive Apps PDF | HTML 31 ago 2023
Certificate ISO5451 CQC Certificate of Product Certification 16 ago 2023
Certificate TUV Certificate for Isolation Devices (Rev. K) 05 ago 2022
Certificate UL Certificate of Compliance File E181974 Vol 4 Sec 6 (Rev. P) 05 ago 2022
Application note Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting (Rev. A) PDF | HTML 17 feb 2022
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 dic 2021
Certificate CSA Certification (Rev. Q) 14 jun 2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28 feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 feb 2020
Functional safety information Isolation in AC Motor Drives: Understanding the IEC 61800-5-1 Safety Standard (Rev. A) 19 sep 2019
Technical article Designing highly efficient, powerful and fast EV charging stations PDF | HTML 06 ago 2019
Analog Design Journal Pushing the envelope with high-performance digital-isolation technology (Rev. A) 22 ago 2018
User guide ISO5852SDW Driving and Protecting SiC and IGBT Power Modules 24 may 2018
Functional safety information Isolation in solar power converters: Understanding the IEC62109-1 safety standar (Rev. A) 18 may 2018
Technical article Why capacitive isolation: a vital building block for sensors in smart cities PDF | HTML 16 ene 2018
Application note Isolation Glossary (Rev. A) 19 sep 2017
Technical article Understanding isolator failure modes for safe isolation PDF | HTML 28 mar 2016
Technical article 7 steps to choose the right isolators for AC motor-drive applications PDF | HTML 24 nov 2015
Analog Design Journal 4Q 2015 Analog Applications Journal 30 oct 2015
Analog Design Journal Common-mode transient immunity for isolated gate drivers 30 oct 2015
Analog Design Journal Pushing the envelope with high-performance digital-isolation technology 30 oct 2015
EVM User's guide ISO5852S Evaluation Module User's Guide (Rev. A) 08 sep 2015
White paper Understanding electromagnetic compliance tests in digital isolators 17 oct 2014
White paper High-voltage reinforced isolation: Definitions and test methodologies 16 oct 2014
Application note Shelf-Life Evaluation of Lead-Free Component Finishes 24 may 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ISO5852SDWEVM-017 — Placa de evaluación de conducción y protección para módulos de potencia SiC e IGBT

The ISO5852SDWEVM-017 is a compact, dual chanel isolated gate driver board providing drive, bias voltages, protection and diagnostic needed for half-bridge Sic MOSFET and IGBT Power Modules in standard 62-mm package. This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in (...)

Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

ISO5852SEVM — Módulo de evaluación de controlador de puerta IGBT/MOSFER aislada reforzada

This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.

Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

ISO5852S IBIS Model

SLLM283.ZIP (33 KB) - IBIS Model
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Modelo de simulación

ISO5852S PSpice Transient Model (Rev. A)

SLLM300A.ZIP (232 KB) - PSpice Model
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Modelo de simulación

ISO5852S TINA-TI Reference Design

SLLM436.TSC (1537 KB) - TINA-TI Reference Design
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Modelo de simulación

ISO5852S TINA-TI SPICE Model

SLLM435.ZIP (31 KB) - TINA-TI Spice Model
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Modelo de simulación

ISO5852S Unencrypted PSPICE Transient Model

SLLM446.ZIP (4 KB) - PSpice Model
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Herramienta de diseño

SLLR117 — ISO5852SDWEVM-017 Design Files

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Drivers de compuerta aislados
ISO5852S — Controlador de puerta aislada monocanal de 5.7 kVrms, 2.5 A/5 A con salida dividida, STO y funciones
Desarrollo de hardware
Placa de evaluación
ISO5852SDWEVM-017 — Placa de evaluación de conducción y protección para módulos de potencia SiC e IGBT
Descargar
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Diseños de referencia

TIDA-01606 — Diseño de referencia de convertidor (tipo T) y PFC de 10 kW, bidireccional, trifásico y de tres nive

This verified reference design provides an overview on how to implement a three-level three-phase SiC based DC:AC T-type inverter stage. Higher switching frequency of 50KHz reduces the size of magnetics for the filter design and enables higher power density. The use of SiC MOSFETs with switching (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00195 — Diseño de referencia de la plataforma de evaluación del controlador de puerta IGBT aislado para el s

The TIDA-00195 reference design consists of a 22kW power stage with TI’s new reinforced isolated IGBT gate driver ISO5852S intended for motor control in various applications. This design allows performance evaluation of the ISO5852S in 3-phase inverter incorporating 1200V rated IGBT modules (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01599 — Diseño de referencia de desconexión segura del par (STO) para accionamientos industriales evaluado p

This reference design outlines a safe torque off (STO) subsystem for a three-phase inverter with CMOS input isolated IGBT gate drivers. The STO subsystem employs a dual-channel architecture (1oo2) with a hardware fault tolerance of 1 (HFT=1). It is implemented following a de-energize trip concept. (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00917 — Diseño de referencia de controlador de puerta para IGBT paralelos con protección contra cortocircuit

Paralleling insulated-gate bipolar transistors (IGBTs) becomes necessary for power conversion equipment with higher output power ratings, where a single IGBT cannot provide the required load current. This reference design implements a reinforced isolated IGBT gate control module to drive (...)
Design guide: PDF
Esquema: PDF
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SOIC (DW) 16 Ultra Librarian
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Pedidos y calidad

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  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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