Inicio Interfaz Serializadores-deserializadores de alta velocidad Serializadores-deserializadores FPD-Link

SN65LVDS86A-Q1

ACTIVO

Receptor FlatLink en catálogo automotriz

Detalles del producto

Function Deserializer Color depth (bpp) 18 Input compatibility LVDS Output compatibility LVCMOS Features Capable to Drive up to 10 meters STP Cable Applications In-vehicle Infotainment (IVI) Rating Automotive Operating temperature range (°C) -40 to 125
Function Deserializer Color depth (bpp) 18 Input compatibility LVDS Output compatibility LVCMOS Features Capable to Drive up to 10 meters STP Cable Applications In-vehicle Infotainment (IVI) Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 3:21 Data Channel Expansion at up to 178.5 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to
    Display With Very Low EMI
  • Three Data Channels and Clock Low-Voltage Differential Channels In
    and 21 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply
  • Tolerates 4-kV Human-Body Model (HBM) ESD
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Standard Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the SN75LVDS86 and NSC DS90C364
  • Improved Jitter Tolerance
  • Qualified for Automotive Applications

  • 3:21 Data Channel Expansion at up to 178.5 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to
    Display With Very Low EMI
  • Three Data Channels and Clock Low-Voltage Differential Channels In
    and 21 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply
  • Tolerates 4-kV Human-Body Model (HBM) ESD
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Standard Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the SN75LVDS86 and NSC DS90C364
  • Improved Jitter Tolerance
  • Qualified for Automotive Applications

The SN65LVDS86A FlatLink™ receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.

The SN65LVDS86A FlatLink™ receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.

Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 1
Tipo Título Fecha
* Data sheet SN65LVDS86A-Q1 Flat Link Receiver datasheet (Rev. A) 16 ene 2012

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (DGG) 48 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos