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TLK10232

ACTIVO

Transceptor de plano posterior de XAUI a 10GBASE-R de doble canal con interruptor de cruce

Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Dual Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet
    Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125
    Gbps Data Rate on the High Speed Side and up to 5 Gbps
    on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables,
    or SFP+ Optical Modules
  • Selectable Reference Clock per Channel with Multiple
    Output Clock Options
  • Integrated Crosspoint Switch Allows for Flexible Signal
    Routing and Redundant Outputs
  • Supports Data Retime Operation
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency
    Patterns, and KR Pseudo-Random Pattern Generation and
    Verification, Square-Wave Generation
  • Two Power Supplies: 1.0V (Core), and 1.5 or 1.8V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization
    to Allow Extended Backplane/Cable Reach on Both High
    Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction,
    Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature
    (–40°C to 85°C)
  • Power Consumption: 800mW per Channel (Nominal)
  • Device Package: 13mm × 13mm, 144-pin PBGA,
    1-mm Ball-Pitch
  • Dual Channel Multi-Rate Transceiver
  • Supports 10GBASE-KR, XAUI, and 1GBASE-KX Ethernet
    Standards
  • Supports all CPRI and OBSAI Data Rates up to 10 Gbps
  • Supports Multi-Rate SERDES Operation with up to 10.3125
    Gbps Data Rate on the High Speed Side and up to 5 Gbps
    on the Low Speed Side
  • Differential CML I/Os on Both High Speed and Low Speed Sides
  • Interface to Backplanes, Passive and Active Copper Cables,
    or SFP+ Optical Modules
  • Selectable Reference Clock per Channel with Multiple
    Output Clock Options
  • Integrated Crosspoint Switch Allows for Flexible Signal
    Routing and Redundant Outputs
  • Supports Data Retime Operation
  • Supports PRBS, CRPAT, CJPAT, High/Low/Mixed-Frequency
    Patterns, and KR Pseudo-Random Pattern Generation and
    Verification, Square-Wave Generation
  • Two Power Supplies: 1.0V (Core), and 1.5 or 1.8V (I/O)
  • No Power Supply Sequencing Requirements
  • Transmit De-emphasis and Receive Adaptive Equalization
    to Allow Extended Backplane/Cable Reach on Both High
    Speed and Low Speed Sides
  • Loss of Signal (LOS) Detection
  • Supports 10G-KR Link Training, Forward Error Correction,
    Auto-Negotiation
  • Jumbo Packet Support
  • JTAG; IEEE 1149.1 Test Interface
  • Industry Standard MDIO Control Interface
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature
    (–40°C to 85°C)
  • Power Consumption: 800mW per Channel (Nominal)
  • Device Package: 13mm × 13mm, 144-pin PBGA,
    1-mm Ball-Pitch

The TLK10232 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

While operating in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

While operating in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates.

The TLK10232 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported.

The TLK10232 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption.

Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.

The TLK10232 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking.

The TLK10232 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10232 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.

The TLK10232 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.

Both TLK10232 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10232 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10232 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.

The TLK10232 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point data transmission systems. This device supports three primary modes. It can be used as a XAUI to 10GBASE-KR transceiver, as a general-purpose 8b/10b multi-rate 4:1, 2:1, or 1:1 serializer/deserializer, or can be used in 1G-KX mode.

While operating in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

While operating in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates.

The TLK10232 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to 3.125 Gbps are supported.

The TLK10232 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of data. Each output port (either high speed or low speed) can be configured to output data coming from any of the device’s input ports. The switching can be initiated through either a hardware pin or through software control, and can be configured to occur either immediately or after the end of the current packet. This allows for switching between data sources without packet corruption.

Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors.

The TLK10232 provides flexible clocking schemes to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes, allowing for asynchronous clocking.

The TLK10232 provides low speed side and high speed side loopback modes for self-test and system diagnostic purposes.

The TLK10232 has built-in pattern generators and verifiers to help in system tests. The device supports generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT, and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the low speed and high speed side are dependent on the operational mode chosen.

The TLK10232 has an integrated loss of signal (LOS) detection function on both high speed and low speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold.

Both TLK10232 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10232 is ideal for interfacing with an FPGA, ASIC, MAC, or network processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing with remote systems through optical fibers, electrical cables, or backplane interfaces. The TLK10232 supports operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.

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Documentación técnica

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Ver todo 4
Tipo Título Fecha
* Data sheet Dual-Channel XAUI/10GBASE-KR Transceiver with Crosspoint datasheet 31 may 2013
Application note 10GBASE-KR Link Optimization with TLK10034 and TLK10232 (Rev. A) 14 mar 2019
User guide TLK10232 EVM GUI User's Guide 07 mar 2013
EVM User's guide TLK10232 EVM User's Guide 07 mar 2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TLK10232EVM — Módulo de evaluación TLK10232EVM de placa base para TLK10232

Motherboard evaluation board for TLK10232 comes with custom-developed GUI and a detailed EVM user guide. This EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of the (...)
Guía del usuario: PDF
Tarjeta secundaria

TLK10XXXSMAEVM — TLK10XXXSMAEVM: placa auxiliar de desconexión SMA para TLK10232

The TLK10XXXSMAEVM SMA breakout daughterboard is used to for evaluation of the low-speed signals on the TLK10232EVM. SMA cables can be connected from the input signals to the output signals to create an external loopback situation, or to standard lab test equipment. The pinout is compatible with (...)

Guía del usuario: PDF
GUI para el módulo de evaluación (EVM)

SLLC435 TLK10232 EVM GUI Software

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Otras interfaces
TLK10232 Transceptor de plano posterior de XAUI a 10GBASE-R de doble canal con interruptor de cruce
Desarrollo de hardware
Placa de evaluación
TLK10232EVM Módulo de evaluación TLK10232EVM de placa base para TLK10232
Modelo de simulación

TLK10232 HSPICE Model

SLLM212.ZIP (9166 KB) - HSpice Model
Modelo de simulación

TLK10232 IBIS Model

SLLM213.ZIP (60 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-00234 — Diseño de referencia XAUI a SFI de doble canal para sistemas con dos o más puertos ópticos SFP+

The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
Test report: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (CTR) 144 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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