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UCC27524A1-Q1

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Controlador de puerta de doble canal de 5 A/5 A con UVLO de 5 V y manipulación de tensión de entrada

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UCC27524A1-Q1

ACTIVO
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Detalles del producto

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power up and power down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (3.5ns and 6ns typical)
  • 1ns typical delay matching between two channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held low when inputs are floating
  • MSOP-8 PowerPad™ package
  • Operating junction temperature range of –40°C to 150°C
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power up and power down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (3.5ns and 6ns typical)
  • 1ns typical delay matching between two channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held low when inputs are floating
  • MSOP-8 PowerPad™ package
  • Operating junction temperature range of –40°C to 150°C

The UCC27524A1-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A1-Q1 device is a variant of the UCC2752x family. The UCC27524A1-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A1-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A1-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A1-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A1-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A1-Q1 devices is available in a MSOP-PowerPAD-8 with exposed pad (DGN) package.

The UCC27524A1-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A1-Q1 device is a variant of the UCC2752x family. The UCC27524A1-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A1-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A1-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A1-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A1-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A1-Q1 devices is available in a MSOP-PowerPAD-8 with exposed pad (DGN) package.
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Documentación técnica

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* Data sheet UCC27524A1-Q1 Dual 5A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. A) PDF | HTML 13 jun 2024
Application note Why use a Gate Drive Transformer? PDF | HTML 04 mar 2024
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 22 ene 2024
Application note Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 22 ene 2024
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 10 nov 2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28 feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 feb 2020
Application note Improving Efficiency of DC-DC Conversion through Layout 07 may 2019
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 18 ene 2019
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 26 nov 2018
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 oct 2018
Application note PFC Design Choice for On Board Charger Designs 24 may 2018
Application brief Reducing Switching Losses in On-Board Chargers for Electric Vehicles 27 mar 2018
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 16 mar 2018

Diseño y desarrollo

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Modelo de simulación

UCC27524 Unencrypted PSpice Transient Model

SLUM510.ZIP (1 KB) - PSpice Model
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Herramienta de cálculo

SLURB22 — UCC2752X Schematic Review Template

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Drivers del lado de tierra
UCC27523 — Controlador de puerta de doble canal (5 A/5 A) con UVLO de 5 V, entradas de inversión y activación UCC27524 — Controlador de puerta de doble canal 5 A/5 A con UVLO de 5 V, activación y coincidencia de retardo d UCC27524A — Controlador de puerta de doble canal de 5 A/5 A con UVLO de 5 V, activación y manipulación de tensió UCC27524A-Q1 — Controlador de puerta de doble canal de 5 A/5 A con UVLO de 5 V y manipulación de tensión de entrada UCC27524A1-Q1 — Controlador de puerta de doble canal de 5 A/5 A con UVLO de 5 V y manipulación de tensión de entrada UCC27525 — Controlador de puerta de doble canal de 5 A/5 A con UVLO de 5 V, activación y entradas de inversión/ UCC27526 — Controlador de puerta de doble canal (5 A/5 A) con UVLO de 5 V, activación y entradas TTL dobles UCC27527 — Controlador de puerta de doble canal (5 A/5 A) con UVLO de 5 V, activación y entradas CMOS dobles UCC27528 — Controlador de puerta de doble canal (5 A/5 A) con UVLO de 5 V, entradas CMOS y activación UCC27528-Q1 — Controlador de puerta de doble canal (5 A/5 A) con UVLO de 5 V y entradas CMOS para automoción
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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HVSSOP (DGN) 8 Ultra Librarian
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Pedidos y calidad

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  • Marcado del dispositivo
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  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
  • Lugar de ensamblaje

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