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UCC27524A-Q1

現行

具有 5-V UVLO 和負輸入電壓處理功能的汽車 5-A/5-A 雙通道閘極驅動器

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產品規格表

UCC27524A-Q1

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results
    • Device temperature grade 1
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power-up and power-down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between 2-channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held in low when inputs are floating
  • SOIC-8 and VSSOP-8 PowerPad™ package options
  • Operating temperature range of –40°C to 150°C
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results
    • Device temperature grade 1
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent enable function for each output
  • TTL and CMOS-compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high-noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO, (ensures glitch-free operation at power-up and power-down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between 2-channels
  • Ability to parallel two outputs for high-drive current
  • Outputs held in low when inputs are floating
  • SOIC-8 and VSSOP-8 PowerPad™ package options
  • Operating temperature range of –40°C to 150°C

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and VSSOP-PowerPAD-8 with exposed pad (DGN) packages.

The UCC27524A-Q1 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524A-Q1 device is a variant of the UCC2752x family. The UCC27524A-Q1 device adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524A-Q1 device is a dual, non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524A-Q1 device is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 17ns). In addition, the drivers feature matched, internal-propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For protection purposes, internal pull-up and pull-down resistors on the input pins of the UCC27524A-Q1 device ensure that outputs are held LOW when input pins are in floating condition. The UCC27524A-Q1 device features enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

The UCC27524A-Q1 devices is available in SOIC-8 (D) and VSSOP-PowerPAD-8 with exposed pad (DGN) packages.
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UCC27624-Q1 現行 具 4V UVLO、30V VDD 和低傳播延遲的車用 5A/5A 雙通道閘極驅動器 Next generation with better negative voltage handling and robustness

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類型 標題 日期
* Data sheet UCC27524A-Q1 Dual 5A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet (Rev. C) PDF | HTML 2024年 6月 13日
Functional safety information UCC27524A-Q1 Functional Safety FIT Rate, FMD and Pin FMA (Rev. A) PDF | HTML 2024年 9月 3日
Application note Why use a Gate Drive Transformer? PDF | HTML 2024年 3月 4日
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 2024年 1月 22日
Application note Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 2024年 1月 22日
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 2021年 11月 10日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application note Improving Efficiency of DC-DC Conversion through Layout 2019年 5月 7日
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 2019年 1月 18日
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 2018年 11月 26日
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 2018年 10月 29日
Application note PFC Design Choice for On Board Charger Designs 2018年 5月 24日
White paper Driving the future of HEV/EV with high-voltage solutions (Rev. B) 2018年 5月 16日
Application brief Reducing Switching Losses in On-Board Chargers for Electric Vehicles 2018年 3月 27日
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 2018年 3月 16日
Technical article Are you on-board? Demystifying EV charging systems PDF | HTML 2017年 7月 31日

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開發板

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模擬型號

UCC27524 PSpice Transient Model

SLUM243.ZIP (28 KB) - PSpice Model
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模擬型號

UCC27524 TINA-TI Transient Reference Design

SLUM257.TSC (89 KB) - TINA-TI Reference Design
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UCC27524 TINA-TI Transient Spice Model

SLUM256.ZIP (8 KB) - TINA-TI Spice Model
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UCC27524 Unencrypted PSpice Transient Model

SLUM510.ZIP (1 KB) - PSpice Model
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計算工具

SLURB22 — UCC2752X Schematic Review Template

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

TIDM-02009 — 經 ASIL D 安全概念評估的高速牽引、雙向 DC/DC 轉換參考設計

此參考設計展現如何以單一 TMS320F28388D 即時 C2000™ MCU 控制 HEV/EV 牽引變流器和雙向 DC-DC 轉換器。牽引控制運用軟體式解析器轉數位轉換器 (RDC) 將馬達驅動至高達 20,000 RPM 的高速。DC-DC 轉換器則採用尖峰電流模式控制 (PCMC) 技術，以及全橋相移式轉換器 (PSFB) 拓撲與同步整流 (SR) 機制。牽引變流器級使用由 UCC5870-Q1 智慧閘極驅動器驅動的碳化矽 (SiC) 功率級。PCMC 波形是使用最先進的 PWM 模組和比較器子系統 (CMPSS)中的內建傾斜補償產生。ASIL (...)
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HVSSOP (DGN) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
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