Inicio Interfaz Circuitos integrados Ethernet Capa física (PHY) Ethernet

DP83TC817S-Q1

ACTIVO

PHY Ethernet 100BASE-T1 para automoción, precisión de tiempo con TC-10 y MACsec

Detalles del producto

Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Number of ports Single Rating Automotive Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Number of ports Single Rating Automotive Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
VQFN (RHA) 36 36 mm² 6 x 6
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG Ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC
    • Auto rollover support for SAK
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal
      • Synchronization Jitter: < ±15ns (options to reduce to ±1ns)
      • Synchronization Offset: < ±30ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • IEEE 802.3bw, OA 100BASE-T1 and TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • MAC Interfaces: MII, RMII, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG Ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC
    • Auto rollover support for SAK
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal
      • Synchronization Jitter: < ±15ns (options to reduce to ±1ns)
      • Synchronization Offset: < ±30ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • IEEE 802.3bw, OA 100BASE-T1 and TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • MAC Interfaces: MII, RMII, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD

The DP83TC817S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility.

The DP83TC817S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The PHY supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC817S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC817S-Q1 integrates IEEE802.1AS / IEEE1588v2 to enable highly accurate time synchronization and hardware time stamping for time-sensitive, real-time controlled applications, with support for encrypted PTP packets.

The DP83TC817S-Q1 supports OA TC-10 low power sleep feature with wake forwarding for reduced system power consumption when communication is not required.

The DP83TC817S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.

The DP83TC817S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility.

The DP83TC817S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The PHY supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC817S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC817S-Q1 integrates IEEE802.1AS / IEEE1588v2 to enable highly accurate time synchronization and hardware time stamping for time-sensitive, real-time controlled applications, with support for encrypted PTP packets.

The DP83TC817S-Q1 supports OA TC-10 low power sleep feature with wake forwarding for reduced system power consumption when communication is not required.

The DP83TC817S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.

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Tipo Título Fecha
* Data sheet DP83TC817S-Q1 Precise and Secure 100BASE-T1 Automotive Ethernet with IEEE802.1AE MACsec, IEEE802.1AS and TC10 Sleep-Wake datasheet (Rev. A) PDF | HTML 30 oct 2024
Application brief Advancing Humanoid Robotics with Single Pair Ethernet PDF | HTML 13 dic 2024
Application note SGMII Troubleshooting Guide PDF | HTML 05 nov 2024
Technical article How Ethernet PHY with hardware synchronization extends the range of automotive radar PDF | HTML 14 jun 2024

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Software de aplicación y estructura

DP83TC817-Q1-DESIGN DP83TC817-Q1 100BASE-T1 PHY with MACsec

DP83TC817-Q1
Productos y hardware compatibles

Productos y hardware compatibles

Productos
Capa física (PHY) Ethernet
DP83TC817S-Q1 PHY Ethernet 100BASE-T1 para automoción, precisión de tiempo con TC-10 y MACsec
Herramienta de simulación

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-020072 — Diseño de referencia de expansión de Ethernet para automoción 100/1000Base-T1 para procesadores J

Este diseño de referencia interactúa con las placas de EVM del procesador Jacinto™ 7 a través del conector en serie de expansión Ethernet. La conectividad Ethernet automotriz se implementa a través de los dispositivos de interfaz física (PHY) Ethernet automotrices de TI. El diseño se implementa con (...)
Design guide: PDF
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Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
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