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DS90C385A

ACTIVO

Transmisor LVDS para pantalla plana de 85 MHz

Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Pin-to-Pin Compatible to DS90C383, DS90C383A and DS90C385
  • No Special Start-Up Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread
  • “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low When Input Clock is Missing and When /PD Pin is Logic High
  • 18 to 87.5 MHz Shift Clock Support
  • Tx Power Consumption < 147 mW (typ) at 87.5MHz Grayscale
  • Tx Power-Down Mode < 60 μW (typ)
  • Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual Pixel).
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.45 Gbps Throughput
  • Up to 306.25Megabyte/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low Profile 56-lead TSSOP Package

All trademarks are the property of their respective owners.

  • Pin-to-Pin Compatible to DS90C383, DS90C383A and DS90C385
  • No Special Start-Up Sequence Required between Clock/Data and /PD Pins. Input Signals (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100kHz Frequency Modulation and Deviations of ±2.5% Center Spread or -5% Down Spread
  • “Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low When Input Clock is Missing and When /PD Pin is Logic High
  • 18 to 87.5 MHz Shift Clock Support
  • Tx Power Consumption < 147 mW (typ) at 87.5MHz Grayscale
  • Tx Power-Down Mode < 60 μW (typ)
  • Supports VGA, SVGA, XGA, SXGA(Dual Pixel), SXGA+(Dual Pixel), UXGA(Dual Pixel).
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 2.45 Gbps Throughput
  • Up to 306.25Megabyte/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low Profile 56-lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.

The DS90C385A transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 306.25Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking support.

The DS90C385A is a pin to pin compatible replacement for DS90C383, DS90C383A and DS90C385. The DS90C385A has additional features and improvements making it an ideal replacement for DS90C383, DS90C383A and DS90C385. family of LVDS Transmitters.

The DS90C385A transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 306.25Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spread Spectrum Clocking support.

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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90C385A 3.3V Prog LVDS Trans 24-Bit FPD Link-87.5 MHz datasheet (Rev. K) 17 abr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 ago 2017
User guide FLINK3V8BT-85 Evaluation Kit (Rev. A) 24 ago 2016
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 ene 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 may 2004
Application note AN-1056 STN Application Using FPD-Link 14 may 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 may 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

FLINK3V8BT-85 — Kit de evaluación para la familia FPD-Link de dispositivos LVDS serializadores y deserializadores

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

Guía del usuario: PDF
Modelo de simulación

DS90C385A IBIS Model

SNLM080.ZIP (7 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Diseños de referencia

TIDA-010013 — Diseño de referencia de puente de visualización RGB a OLDI/LVDS para procesadores Sitara™

Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (DGG) 56 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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