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DS90CF384A

ACTIVO

Receptor LVDS de +3.3 V para enlace de pantalla plana (FPD) de 24 bits y 65 MHz

Detalles del producto

Function Deserializer Color depth (bpp) 24 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
Function Deserializer Color depth (bpp) 24 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • 20 to 65 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best-in-Class Set & Hold Times on RxOUTPUTs
  • Rx Power Consumption <142 mW (typ) @65MHz Grayscale
  • Rx Power-down Mode <200μW (max)
  • ESD Rating >7 kV (HBM), >700V (EIAJ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-lead or 48-lead Packages

All trademarks are the property of their respective owners.

  • 20 to 65 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best-in-Class Set & Hold Times on RxOUTPUTs
  • Rx Power Consumption <142 mW (typ) @65MHz Grayscale
  • Rx Power-down Mode <200μW (max)
  • ESD Rating >7 kV (HBM), >700V (EIAJ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-lead or 48-lead Packages

All trademarks are the property of their respective owners.

The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic.

The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers' outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic.

The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90CF384A/364A 3.3V LVDS Rcvr 24Bit FPD Link 65MHz/18Bit FPD Link - 65 MHz datasheet (Rev. I) 19 abr 2013
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 ago 2017
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 ene 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 may 2004
Application note AN-1056 STN Application Using FPD-Link 14 may 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 may 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

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The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

Guía del usuario: PDF
Herramienta de simulación

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (DGG) 56 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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